[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Enable LPC bus interface
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Sat Apr 23 23:56:31 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14469
-gerrit
commit 91bf5c0f94bb96e0b90d6b354cfa50cb15fabb73
Author: Divya Sasidharan <divya.s.sasidharan at intel.com>
Date: Fri Feb 5 11:27:44 2016 -0800
soc/intel/apollolake: Enable LPC bus interface
Enable LPC serial IRQ as well as adds some LPC constants.
Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2
Signed-off-by: Divya Sasidharan <divya.s.sasidharan at intel.com>
Signed-off-by: Freddy Paul <freddy.paul at intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/chip.h | 9 ++++++
src/soc/intel/apollolake/include/soc/lpc.h | 40 +++++++++++++++++++++++++
src/soc/intel/apollolake/include/soc/pci_devs.h | 3 ++
src/soc/intel/apollolake/lpc.c | 22 +++++++++++++-
src/soc/intel/apollolake/romstage.c | 28 +++++++++++++++++
5 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 9d2bc46..32d93de 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -32,6 +32,15 @@ struct soc_intel_apollolake_config {
uint8_t pcie_rp3_clkreq_pin;
uint8_t pcie_rp4_clkreq_pin;
uint8_t pcie_rp5_clkreq_pin;
+
+ /* Generic IO decode ranges */
+ uint32_t gen1_dec;
+ uint32_t gen2_dec;
+ uint32_t gen3_dec;
+ uint32_t gen4_dec;
+
+ /* LPC port ranges */
+ uint16_t lpc_dec;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h
new file mode 100644
index 0000000..2125f4a
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/lpc.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_LPC_H
+#define _SOC_APOLLOLAKE_LPC_H
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define SERIRQ_CNTL 0x64 /* Serial IRQ Control Register */
+#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define LPC_EN 0x82 /* LPC IF Enables Register */
+#define LPC_EN_COMA (1 << 0) /* COM port A */
+#define LPC_EN_COMB (1 << 1) /* COM port B */
+#define LPC_EN_PARP (1 << 2) /* Parallel port */
+#define LPC_EN_FLP (1 << 3) /* Floppy */
+#define LPC_EN_LGAME (1 << 8) /* Low Gameport, 0x200-0x207 */
+#define LPC_EN_HGAME (1 << 9) /* High Gameport, 0x208-0x20f */
+#define LPC_EN_KB (1 << 10) /* Keyboard, 0x60, 0x64 */
+#define LPC_EN_MC1 (1 << 11) /* Microcontroller #1, 0x62, 0x66 */
+#define LPC_EN_MC2 (1 << 13) /* Microcontroller #2, 0x4e, 0x4f */
+#define LPC_EN_SIO (1 << 12) /* Super IO, 0x2e, 0x2f */
+
+#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC 0x8C /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
+
+#endif //_SOC_APOLLOLAKE_LPC_H
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index 7b8caaf..ae80a04 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -48,8 +48,11 @@
#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+#define LPC_SLOT 0x1f
+
#define P2SB_DEV PCI_DEV(0, 0xd, 0)
#define PMC_DEV PCI_DEV(0, 0xd, 1)
#define SPI_DEV PCI_DEV(0, 0xd, 2)
+#define LPC_DEV PCI_DEV(0, LPC_SLOT, 0)
#endif
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 902ada2..45532b2 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
* (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -20,6 +20,25 @@
#include <device/pci_ids.h>
#include <soc/acpi.h>
#include <soc/pci_ids.h>
+#include <reg_script.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/lpc.h>
+#include "chip.h"
+
+static const struct reg_script lpc_serirq_enable[] = {
+ /* Setup SERIRQ, enable continuous mode */
+ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+ REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
+#endif
+ REG_SCRIPT_END
+};
+
+static void lpc_init(struct device *dev)
+{
+ reg_script_run_on_dev(dev, lpc_serirq_enable);
+}
+
static void soc_lpc_add_io_resources(device_t dev)
{
@@ -46,6 +65,7 @@ static struct device_operations device_ops = {
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.write_acpi_tables = southbridge_write_acpi_tables,
+ .init = &lpc_init
};
static const struct pci_driver soc_lpc __pci_driver = {
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 640026a..1c016a0 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -23,19 +23,45 @@
#include <cbmem.h>
#include <console/console.h>
#include <device/pci_def.h>
+#include <device/device.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <device/resource.h>
#include <string.h>
#include <soc/iomap.h>
#include <soc/intel/common/mrc_cache.h>
+#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/northbridge.h>
#include <soc/romstage.h>
#include <soc/uart.h>
+#include <soc/intel/apollolake/chip.h>
#define FIT_POINTER (0x100000000ULL - 0x40)
+static void enable_lpc_decode(void)
+{
+ const struct device *lpc;
+ const struct soc_intel_apollolake_config *config;
+
+ lpc = dev_find_slot(0, PCI_DEVFN(LPC_SLOT, 0));
+
+ if (!lpc)
+ return;
+ if (lpc->chip_info)
+ config = lpc->chip_info;
+
+ /* Enable requested fixed IO decode ranges */
+ pci_write_config16(LPC_DEV, LPC_EN, config->lpc_dec);
+
+ /* Enable generic IO decode ranges */
+ pci_write_config32(LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
+ pci_write_config32(LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
+ pci_write_config32(LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
+ pci_write_config32(LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
+}
+
+
/*
* Enables several BARs and devices which are needed for memory init
* - MCH_BASE_ADDR is needed in order to talk to the memory controller
@@ -63,6 +89,8 @@ static void soc_early_romstage_init(void)
/* Enable decoding for HPET. Needed for FSP global pointer storage */
pci_write_config32(P2SB_DEV, 0x60, 1<<7);
+
+ enable_lpc_decode();
}
static void disable_watchdog(void)
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