[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Enable LPC bus interface

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14469

-gerrit

commit 912a31e08db6338dbc3a6862babdd4b87da1f3bd
Author: Divya Sasidharan <divya.s.sasidharan at intel.com>
Date:   Fri Feb 5 11:27:44 2016 -0800

    soc/intel/apollolake: Enable LPC bus interface
    
    Enables LPC serial IRQ as well as adds some LPC constants.
    
    Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2
    Signed-off-by: Divya Sasidharan <divya.s.sasidharan at intel.com>
    Signed-off-by: Freddy Paul <freddy.paul at intel.com>
---
 src/soc/intel/apollolake/chip.h            |  4 ++++
 src/soc/intel/apollolake/include/soc/lpc.h | 30 ++++++++++++++++++++++++++++++
 src/soc/intel/apollolake/lpc.c             | 23 ++++++++++++++++++++++-
 3 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 9d2bc46..a5c7ac2 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -32,6 +32,10 @@ struct soc_intel_apollolake_config {
 	uint8_t pcie_rp3_clkreq_pin;
 	uint8_t pcie_rp4_clkreq_pin;
 	uint8_t pcie_rp5_clkreq_pin;
+
+	/* Generic IO decode ranges */
+	uint32_t gen1_dec;
+	uint32_t gen2_dec;
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h
new file mode 100644
index 0000000..87e92c3
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/lpc.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_LPC_H
+#define _SOC_APOLLOLAKE_LPC_H
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define SERIRQ_CNTL		0x64 /* Serial IRQ Control Register */
+#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define LPC_EN			0x82 /* LPC IF Enables Register */
+#define MC_LPC_EN		(1 << 11) /* 0x62/0x66 */
+#define KBC_LPC_EN		(1 << 10) /* 0x60/0x64 */
+#define GAMEL_LPC_EN		(1 << 8)  /* 0x200/0x207 */
+#define LPC_GEN1_DEC		0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC		0x88 /* LPC IF Generic Decode Range 2 */
+
+#endif //_SOC_APOLLOLAKE_LPC_H
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 902ada2..aadf18b 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2015 Intel Corp.
  * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -20,6 +20,25 @@
 #include <device/pci_ids.h>
 #include <soc/acpi.h>
 #include <soc/pci_ids.h>
+#include <reg_script.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/lpc.h>
+#include "chip.h"
+
+static const struct reg_script lpc_serirq_enable[] = {
+	/* Setup SERIRQ, enable continuous mode */
+	REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
+#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+	REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
+#endif
+	REG_SCRIPT_END
+};
+
+static void lpc_init(struct device *dev)
+{
+	reg_script_run_on_dev(dev, lpc_serirq_enable);
+}
+
 
 static void soc_lpc_add_io_resources(device_t dev)
 {
@@ -45,7 +64,9 @@ static struct device_operations device_ops = {
 	.read_resources = &soc_lpc_read_resources,
 	.set_resources = &pci_dev_set_resources,
 	.enable_resources = &pci_dev_enable_resources,
+	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
 	.write_acpi_tables = southbridge_write_acpi_tables,
+	.init = &lpc_init
 };
 
 static const struct pci_driver soc_lpc __pci_driver = {