[coreboot-gerrit] New patch to review for coreboot: nb/intel/sandybridge/raminit: fix regression "always use mrccache"

Patrick Rudolph (siro@das-labor.org) gerrit at coreboot.org
Wed Apr 20 18:12:24 CEST 2016


Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14439

-gerrit

commit 3c4ed755143500c0bba3f1be4f81a9389421a9c5
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Wed Apr 20 18:00:27 2016 +0200

    nb/intel/sandybridge/raminit: fix regression "always use mrccache"
    
    Fix regression introduced by:
    Ib48fe8380446846df17d37b22968f7d4fd6b9b13
    
    Don't run channel_test on S3 resume as it overrides memory
    that might be in use.
    Fixes MCE events reported by the GNU/Linux kernel that
    low memory has been modified.
    
    Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/northbridge/intel/sandybridge/raminit.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 042898d..195f3fc 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -4038,7 +4038,7 @@ static void restore_timings(ramctr_timing * ctrl)
 }
 
 static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
-		int me_uma_size)
+		int s3_resume, int me_uma_size)
 {
 	int err;
 
@@ -4148,9 +4148,14 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
 
 	write_controller_mr(ctrl);
 
-	err = channel_test(ctrl);
-	if (err)
-		return err;
+	if (!s3_resume) {
+		/* The function channel_test overrides low memory
+		 * resulting in MCE events reported by the GNU/Linux kernel
+		 * on S3 resume. */
+		err = channel_test(ctrl);
+		if (err)
+			return err;
+	}
 
 	return 0;
 }
@@ -4228,7 +4233,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck,
 		printk(BIOS_DEBUG, "Trying stored timings.\n");
 		memcpy(&ctrl, ctrl_cached, sizeof(ctrl));
 
-		err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size);
+		err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);
 		if (err) {
 			/* no need to erase bad mrc cache here, it gets overritten on
 			 * successful boot. */
@@ -4243,7 +4248,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck,
 		/* Get DDR3 SPD data */
 		dram_find_spds_ddr3(spds, &ctrl);
 
-		err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size);
+		err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);
 	}
 	if (err)
 		die("raminit failed");



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