[coreboot-gerrit] Patch set updated for coreboot: arch/x86: remove low coreboot table support

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14432

-gerrit

commit 3b204400cb63bca62011a5d697a9c69f22b668ed
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Apr 19 16:11:22 2016 -0500

    arch/x86: remove low coreboot table support
    
    In addition to being consistent with all other architectures,
    all chipsets support cbmem so the low coreboot table path is
    stale and never taken.  Also it's important to note the memory
    written in to that low area of memory wasn't automatically
    reserved unless that path was taken. To that end remove
    low coreboot table support for x86.
    
    Change-Id: Ib96338cf3024e3aa34931c53a7318f40185be34c
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/tables.c    |  7 ++-----
 src/lib/coreboot_table.c | 15 +--------------
 2 files changed, 3 insertions(+), 19 deletions(-)

diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
index 309ac16..b36078d 100644
--- a/src/arch/x86/tables.c
+++ b/src/arch/x86/tables.c
@@ -183,7 +183,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end)
 void write_tables(void)
 {
 	unsigned long low_table_start, low_table_end;
-	unsigned long rom_table_start, rom_table_end;
+	unsigned long rom_table_end;
 
 	/* Even if high tables are configured, some tables are copied both to
 	 * the low and the high area, so payloads and OSes don't need to know
@@ -191,7 +191,6 @@ void write_tables(void)
 	 */
 	unsigned long high_table_pointer;
 
-	rom_table_start = 0xf0000;
 	rom_table_end =   0xf0000;
 
 	/* Start low addr at 0x500, so we don't run into conflicts with the BDA
@@ -242,8 +241,6 @@ void write_tables(void)
 			printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
 				new_high_table_pointer - high_table_pointer);
 	} else {
-		/* The coreboot table must be in 0-4K or 960K-1M */
-		write_coreboot_table(low_table_start, low_table_end,
-				     rom_table_start, rom_table_end);
+		printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
 	}
 }
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 18e8b34..091ceaf 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -447,7 +447,7 @@ static unsigned long lb_table_fini(struct lb_header *head)
 
 unsigned long write_coreboot_table(
 	unsigned long low_table_start, unsigned long low_table_end,
-	unsigned long rom_table_start, unsigned long rom_table_end)
+	unsigned long rom_table_start __unused, unsigned long rom_table_end)
 {
 	struct lb_header *head;
 
@@ -468,10 +468,6 @@ unsigned long write_coreboot_table(
 		rom_table_end);
 
 	head = lb_table_init(rom_table_end);
-	rom_table_end = (unsigned long)head;
-	printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
-	rom_table_end = ALIGN(rom_table_end, (64 * 1024));
-	printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end);
 
 #if CONFIG_USE_OPTION_TABLE
 	{
@@ -500,15 +496,6 @@ unsigned long write_coreboot_table(
 		bootmem_add_range(low_table_start, size, LB_MEM_TABLE);
 	}
 
-	/* Record the pirq table, acpi tables, and maybe the mptable. However,
-	 * these only need to be added when the rom_table is sitting below
-	 * 1MiB. If it isn't that means high tables are being written.
-	 * The code below handles high tables correctly. */
-	if (rom_table_end <= (1 << 20)) {
-		uint64_t size = rom_table_end - rom_table_start;
-		bootmem_add_range(rom_table_start, size, LB_MEM_TABLE);
-	}
-
 	/* No other memory areas can be added after the memory table has been
 	 * committed as the entries won't show up in the serialize mem table. */
 	bootmem_write_memory_table(lb_memory(head));