[coreboot-gerrit] New patch to review for coreboot: kontron/come-bip2: Add initial CPLD support

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14403

-gerrit

commit 40b037b78d6394db34e740a91cf0a9f689262ced
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Mon Apr 18 17:56:43 2016 -0700

    kontron/come-bip2: Add initial CPLD support
    
    This adds support for talking to the Kontron CPLD.
    Right now, the only supported function is to dump the
    CPLD's registers.
    
    Change-Id: I2721346e2dadc0f30795f395902994773e730bbf
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 src/mainboard/kontron/come-bip2/Makefile.inc |  1 +
 src/mainboard/kontron/come-bip2/cpld.c       | 74 ++++++++++++++++++++++++++++
 src/mainboard/kontron/come-bip2/cpld.h       | 29 +++++++++++
 src/mainboard/kontron/come-bip2/romstage.c   |  4 ++
 4 files changed, 108 insertions(+)

diff --git a/src/mainboard/kontron/come-bip2/Makefile.inc b/src/mainboard/kontron/come-bip2/Makefile.inc
index 5aaf562..413cc80 100644
--- a/src/mainboard/kontron/come-bip2/Makefile.inc
+++ b/src/mainboard/kontron/come-bip2/Makefile.inc
@@ -20,3 +20,4 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
 
 romstage-y += gpio.c
+romstage-y += cpld.c
diff --git a/src/mainboard/kontron/come-bip2/cpld.c b/src/mainboard/kontron/come-bip2/cpld.c
new file mode 100644
index 0000000..d7b8453
--- /dev/null
+++ b/src/mainboard/kontron/come-bip2/cpld.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <lib.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include "cpld.h"
+
+#define CPLD_IDX	0xa80
+#define CPLD_DATA	0xa81
+
+u8 cpld_read8(u8 idx)
+{
+	outb(idx, CPLD_IDX);
+	return inb(CPLD_DATA);
+}
+
+u16 cpld_read16(u8 idx)
+{
+	return cpld_read8(idx) | (cpld_read8(idx + 1) << 8);
+}
+
+u32 cpld_read32(u8 idx)
+{
+	return cpld_read16(idx) | (cpld_read16(idx + 2) << 16);
+}
+
+void cpld_write8(u8 idx, u8 value)
+{
+	outb(idx, CPLD_IDX);
+	outb(value, CPLD_DATA);
+}
+
+void cpld_write16(u8 idx, u16 value)
+{
+	cpld_write8(idx, (u8)value);
+	cpld_write8(idx + 1, (u8)(value >> 8));
+}
+
+void cpld_write32(u8 idx, u32 value)
+{
+	cpld_write16(idx, (u16)value);
+	cpld_write16(idx + 2, (u16)(value >> 16));
+}
+
+void cpld_dump(void)
+{
+	u8 data[256];
+	int i;
+
+	for (i = 0; i <= 0xff; i++)
+		data[i] = cpld_read8(i);
+
+	printk(BIOS_DEBUG, "CPLD registers:\n");
+	hexdump(data, 256);
+	printk(BIOS_DEBUG, "\n\n");
+
+	cpld_write8(0x08, 0x00);
+}
+
+
diff --git a/src/mainboard/kontron/come-bip2/cpld.h b/src/mainboard/kontron/come-bip2/cpld.h
new file mode 100644
index 0000000..6e8ae4a
--- /dev/null
+++ b/src/mainboard/kontron/come-bip2/cpld.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CPLD_H__
+#define __CPLD_H__
+
+#include <stdint.h>
+
+u8 cpld_read8(u8 idx);
+u16 cpld_read16(u8 idx);
+u32 cpld_read32(u8 idx);
+void cpld_write8(u8 idx, u8 value);
+void cpld_write16(u8 idx, u16 value);
+void cpld_write32(u8 idx, u32 value);
+void cpld_dump(void);
+
+#endif
diff --git a/src/mainboard/kontron/come-bip2/romstage.c b/src/mainboard/kontron/come-bip2/romstage.c
index fcdeb3c..84fc4b9 100644
--- a/src/mainboard/kontron/come-bip2/romstage.c
+++ b/src/mainboard/kontron/come-bip2/romstage.c
@@ -37,6 +37,7 @@
 #include <halt.h>
 #include <tpm.h>
 #include <cbfs.h>
+#include "cpld.h"
 
 #include <southbridge/intel/bd82x6x/chip.h>
 
@@ -170,6 +171,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		},
 	};
 	*pei_data = pei_data_template;
+
+	//
+	cpld_dump();
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {