[coreboot-gerrit] Patch set updated for coreboot: A try to add i945G based board (Please Don't merge). I lost the serial connection
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Sun Apr 17 19:28:53 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/9971
-gerrit
commit 9b9852c721383b7df4e9bf804b573704e805a216
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Fri Apr 15 16:32:15 2016 +0200
A try to add i945G based board (Please Don't merge).
I lost the serial connection
Change-Id: I97401a39a958a17f2f9120539362e3fa7819a742
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/nec/945g-m4/Kconfig | 45 +++++
src/mainboard/nec/945g-m4/Kconfig.name | 2 +
src/mainboard/nec/945g-m4/Makefile.inc | 2 +
src/mainboard/nec/945g-m4/acpi/ec.asl | 16 ++
src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 95 +++++++++
src/mainboard/nec/945g-m4/acpi/platform.asl | 86 ++++++++
src/mainboard/nec/945g-m4/acpi/superio.asl | 88 +++++++++
src/mainboard/nec/945g-m4/acpi/thermal.asl | 89 +++++++++
src/mainboard/nec/945g-m4/acpi/x4x_pci_irqs.asl | 79 ++++++++
src/mainboard/nec/945g-m4/acpi_tables.c | 43 ++++
src/mainboard/nec/945g-m4/board_info.txt | 7 +
src/mainboard/nec/945g-m4/cstates.c | 26 +++
src/mainboard/nec/945g-m4/devicetree.cb | 124 ++++++++++++
src/mainboard/nec/945g-m4/dsdt.asl | 40 ++++
src/mainboard/nec/945g-m4/hda_verb.c | 20 ++
src/mainboard/nec/945g-m4/mainboard.c | 40 ++++
src/mainboard/nec/945g-m4/romstage.c | 240 +++++++++++++++++++++++
src/mainboard/nec/945g-m4/superio_hwm.c | 174 ++++++++++++++++
src/mainboard/nec/945g-m4/superio_hwm.h | 21 ++
19 files changed, 1237 insertions(+)
diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig
new file mode 100644
index 0000000..1aa3a80
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Kconfig
@@ -0,0 +1,45 @@
+if BOARD_NEC_945G_M4
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_X4X
+ #select CHECK_SLFRCS_ON_RESUME
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627EHG
+ select HAVE_ACPI_TABLES
+ #select HAVE_PIRQ_TABLE
+ #select HAVE_MP_TABLE
+ #select HAVE_OPTION_TABLE
+ #select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_512
+ #select CHANNEL_XOR_RANDOMIZATION
+
+config MAINBOARD_DIR
+ string
+ default "nec/945g-m4"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "945G-M4"
+
+config CONFIG_CBFS_SIZE
+ hex
+ default 0x80000
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+#config IRQ_SLOT_COUNT
+# int
+# default 18
+
+#config MAX_CPUS
+# int
+# default 4
+
+#config VGA_BIOS_FILE
+# string
+# default "amipci_01.20"
+endif # BOARD_NEC_945G_M4
diff --git a/src/mainboard/nec/945g-m4/Kconfig.name b/src/mainboard/nec/945g-m4/Kconfig.name
new file mode 100644
index 0000000..46571f0
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_NEC_945G_M4
+ bool "945G-M"
diff --git a/src/mainboard/nec/945g-m4/Makefile.inc b/src/mainboard/nec/945g-m4/Makefile.inc
new file mode 100644
index 0000000..0b70b89
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Makefile.inc
@@ -0,0 +1,2 @@
+ramstage-y += superio_hwm.c
+ramstage-y += cstates.c
diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl
new file mode 100644
index 0000000..6bb1dfc
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ec.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*to make the compiler happy*/
diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..a16f807
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 16},
+
+ Package() { 0x0001ffff, 0, 0, 20},
+ Package() { 0x0001ffff, 1, 0, 21},
+ Package() { 0x0001ffff, 2, 0, 22},
+ Package() { 0x0001ffff, 3, 0, 23},
+
+ Package() { 0x0002ffff, 0, 0, 21},
+ Package() { 0x0002ffff, 1, 0, 22},
+ Package() { 0x0002ffff, 2, 0, 23},
+ Package() { 0x0002ffff, 3, 0, 20},
+
+ Package() { 0x0003ffff, 0, 0, 22},
+ Package() { 0x0003ffff, 1, 0, 23},
+ Package() { 0x0003ffff, 2, 0, 20},
+ Package() { 0x0003ffff, 3, 0, 21},
+
+ Package() { 0x0004ffff, 0, 0, 23},
+ Package() { 0x0004ffff, 1, 0, 20},
+ Package() { 0x0004ffff, 2, 0, 21},
+ Package() { 0x0004ffff, 3, 0, 22},
+
+ Package() { 0x0005ffff, 0, 0, 19},
+ Package() { 0x0005ffff, 1, 0, 18},
+ Package() { 0x0005ffff, 2, 0, 17},
+ Package() { 0x0005ffff, 3, 0, 16},
+
+ Package() { 0x0006ffff, 0, 0, 18},
+ Package() { 0x0006ffff, 1, 0, 17},
+ Package() { 0x0006ffff, 2, 0, 16},
+ Package() { 0x0006ffff, 3, 0, 19},
+
+ Package() { 0x0009ffff, 0, 0, 21},
+ Package() { 0x0009ffff, 1, 0, 22},
+ Package() { 0x0009ffff, 2, 0, 23},
+ Package() { 0x0009ffff, 3, 0, 20},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
+
+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+ Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+ })
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl
new file mode 100644
index 0000000..c211c08
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/platform.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Call a trap so SMI can prepare for Sleep as well.
+ // TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl
new file mode 100644
index 0000000..b5957c5
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/superio.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+Device (SIO1)
+{
+ Name (_HID, EISAID("PNP0A05"))
+ Name (_UID, 1)
+
+ Device (UAR1)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 1)
+ Name(_DDN, "COM1")
+
+ Method (_STA, 0)
+ {
+ // always enable for now
+ Return (0x0f)
+ }
+
+ Method (_DIS, 0) { /* NOOP */ }
+
+ Name (_PRS, ResourceTemplate() {
+ StartDependentFn(0, 1) {
+ IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+ IRQNoFlags() { 4 }
+ } EndDependentFn()
+ })
+
+ Method (_CRS, 0)
+ {
+ Return(ResourceTemplate() {
+ IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
+ IRQNoFlags() { 4 }
+ })
+ }
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+
+ Device (UAR2)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 2)
+ Name(_DDN, "COM2")
+
+ Method (_STA, 0)
+ {
+ // always enable for now
+ Return (0x0f)
+ }
+
+ Method (_DIS, 0) { /* NOOP */ }
+
+ Name (_PRS, ResourceTemplate() {
+ StartDependentFn(0, 1) {
+ IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+ IRQNoFlags() { 3 }
+ } EndDependentFn()
+ })
+
+ Method (_CRS, 0)
+ {
+ Return(ResourceTemplate() {
+ IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
+ IRQNoFlags() { 3 }
+ })
+ }
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl
new file mode 100644
index 0000000..ef77046
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+
+ // FIXME these could/should be read from the
+ // GNVS area, so they can be controlled by
+ // coreboot
+ Name(TC1V, 0x04)
+ Name(TC2V, 0x03)
+ Name(TSPV, 0x64)
+
+ // At which temperature should the OS start
+ // active cooling?
+ Method (_AC0, 0, Serialized)
+ {
+ Return (0xf5c) // Value for Rocky
+ }
+
+ // Method (_AC1, 0, Serialized)
+ // {
+ // Return (0xf5c)
+ // }
+
+ // Critical shutdown temperature
+ Method (_CRT, 0, Serialized)
+ {
+ Return (Add (0x0aac, 0x50)) // FIXME
+ }
+
+ // CPU throttling start temperature
+ Method (_PSV, 0, Serialized)
+ {
+ Return (0xaaf) // FIXME
+ }
+
+ // Get DTS Temperature
+ Method (_TMP, 0, Serialized)
+ {
+ Return (0xaac) // FIXME
+ }
+
+ // Processors used for active cooling
+ Method (_PSL, 0, Serialized)
+ {
+ If (MPEN) {
+ Return (Package() {\_PR.CP01, \_PR.CP02})
+ }
+ Return (Package() {\_PR.CP01})
+ }
+
+ // TC1 value for passive cooling
+ Method (_TC1, 0, Serialized)
+ {
+ Return (TC1V)
+ }
+
+ // TC2 value for passive cooling
+ Method (_TC2, 0, Serialized)
+ {
+ Return (TC2V)
+ }
+
+ // Sampling period for passive cooling
+ Method (_TSP, 0, Serialized)
+ {
+ Return (TSPV)
+ }
+
+
+ }
+}
diff --git a/src/mainboard/nec/945g-m4/acpi/x4x_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/x4x_pci_irqs.asl
new file mode 100644
index 0000000..8fca85f
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/x4x_pci_irqs.asl
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for i945G */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, 0, 10 },
+ Package() { 0x0001ffff, 1, 0, 11 },
+ Package() { 0x0001ffff, 2, 0, 12 },
+ Package() { 0x0001ffff, 3, 0, 13 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 10 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 10 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 10 },
+ Package() { 0x001cffff, 1, 0, 11 },
+ Package() { 0x001cffff, 2, 0, 12 },
+ Package() { 0x001cffff, 3, 0, 13 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, 0, 17 },
+ Package() { 0x001dffff, 1, 0, 19 },
+ Package() { 0x001dffff, 2, 0, 13 },
+ Package() { 0x001dffff, 3, 0, 12 },
+ // AC97/IDE 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, 0, 11 },
+ Package() { 0x001effff, 1, 0, 24 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, 0, 12 },
+ Package() { 0x001fffff, 1, 0, 13 },
+ })
+ } Else {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ // AC97/IDE 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c
new file mode 100644
index 0000000..8708f41
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi_tables.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+
+#include "southbridge/intel/i82801gx/nvs.h"
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+
+ gnvs->pwrs = 1; /* Power state (AC = 1) */
+ gnvs->lptp = 0; /* LPT port */
+ gnvs->fdcp = 0; /* Floppy Disk Controller */
+ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
+ gnvs->apic = 1; /* Enable APIC */
+ gnvs->mpen = 1; /* Enable Multi Processing */
+
+ /* Enable both COM ports */
+ gnvs->cmap = 0x01;
+ gnvs->cmbp = 0x01;
+}
diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt
new file mode 100644
index 0000000..609899a
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/board_info.txt
@@ -0,0 +1,7 @@
+Board name:945G-M4 (Rev: B)
+Category: desktop
+Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=default&source=1409
+ROM package: PLCC
+ROM protocol: FWH
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/nec/945g-m4/cstates.c b/src/mainboard/nec/945g-m4/cstates.c
new file mode 100644
index 0000000..4d9f4ab
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/cstates.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+
+static acpi_cstate_t cst_entries[] = {};
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb
new file mode 100644
index 0000000..05508d9
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/devicetree.cb
@@ -0,0 +1,124 @@
+chip northbridge/intel/x4x
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x
+ device lapic 0xACAC off end
+ end
+ end
+ device domain 0 on
+ device pci 00.0 on end # 82945G/GZ/P/PL Memory Controller Hub [8086:2770]
+ device pci 02.0 on end # 82945G/GZ Integrated Graphics Controller [8086:2772]
+ chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x8a"
+ register "pirqb_routing" = "0x85"
+ register "pirqc_routing" = "0x8a"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x87"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi13_routing" = "1"
+ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x1"
+
+ device pci 1c.0 on end # PCI Express Gigabit Ethernet Controller [10ec:8168]
+ device pci 1d.0 on end # NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
+ device pci 1d.1 on end # NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9]
+ device pci 1d.2 on end # NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca]
+ device pci 1d.3 on end # NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb]
+ device pci 1d.7 on end # NM10/ICH7 Family USB2 EHCI Controller [8086:27cc]
+ device pci 1e.0 on end # 82801 PCI Bridge [8086:244e]
+ device pci 1e.2 on end # 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de]
+ device pci 1f.0 on # 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8]
+
+ chip superio/winbond/w83627ehg # Super I/O Winbond
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+
+ device pnp 2e.3 off # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ irq 0xf0 = 0x82
+ end
+
+ device pnp 2e.106 on # Serial flash interface
+ io 0x60 = 0x100
+ end
+
+ device pnp 2e.007 on # GPIO 1
+ end
+
+ device pnp 2e.107 off # Game port
+ io 0x60 = 0x201
+ end
+
+ device pnp 2e.207 on # MIDI
+ io 0x62 = 0x330
+ irq 0x70 = 0xa
+ end
+
+ device pnp 2e.307 on # GPIO 6
+ end
+
+ device pnp 2e.8 off # WDTO#, PLED
+ end
+
+ device pnp 2e.009 on # GPIO 2
+ end
+
+ device pnp 2e.109 on # GPIO 3
+ end
+
+ device pnp 2e.209 on # GPIO 4
+ end
+
+ device pnp 2e.309 on # GPIO 5
+ end
+
+ device pnp 2e.a on # ACPI
+ end
+
+ device pnp 2e.b on # Hardware monitor
+ io 0x60 = 0xa10
+ irq 0x70 = 0
+ end
+
+ end # Winbond
+ end # LPC
+
+ device pci 1f.1 on end # 82801G (ICH7 Family) IDE Controller [8086:27df]
+ device pci 1f.2 on end # NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0]
+ device pci 1f.3 on end # NM10/ICH7 Family SMBus Controller [8086:27da]
+ end # i82801gx
+ end # domain 0
+end
diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl
new file mode 100644
index 0000000..77c968a
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/dsdt.asl
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/i82801gx/i82801gx.h>
+
+DefinitionBlock ("dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x00000108) // OEM revision
+{
+ // Some generic macros
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+ #include "acpi/platform.asl"
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/x4x/acpi/x4x.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/nec/945g-m4/hda_verb.c b/src/mainboard/nec/945g-m4/hda_verb.c
new file mode 100644
index 0000000..d925949
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/hda_verb.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[0] = {};
+const u32 pc_beep_verbs[0] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c
new file mode 100644
index 0000000..7942580
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/mainboard.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#include <drivers/intel/gma/int15.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include "superio_hwm.h"
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ install_intel_vga_int15_handler(
+ GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT,
+ 3);
+ hwm_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c
new file mode 100644
index 0000000..7157f8b
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/romstage.c
@@ -0,0 +1,240 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2014 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/romstage.h>
+#include <lib.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627ehg/w83627ehg.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <halt.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+
+static void setup_ich7_gpios(void)
+{
+
+ printk(BIOS_DEBUG, "GPIOS...");
+ /* General Registers */
+ outl(0x1f9fffc3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+ outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+ outl(0xebffffbf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ /* Output Control Registers */
+ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
+ /* Input Control Registers */
+ outl(0x0000af03, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+ outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
+ outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
+ outl(0x000000f7, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
+}
+
+static void ich7_enable_lpc(void)
+{
+ // Enable Serial IRQ
+ pci_write_config8(LPC_DEV, 0x64, 0xd0);
+ // LPC I/O decode range
+ pci_write_config16(LPC_DEV, 0x80, 0x0010);
+ // LPC Interface Enables
+ pci_write_config16(LPC_DEV, 0x82, 0x340f);
+ // GEN1_DEC. LPC interface generic decode Rang1
+ pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
+ // GEN2_DEC. LPC interface generic decode Rang2
+ pci_write_config32(LPC_DEV, 0x88, 0x00fc4701);
+
+}
+
+static void rcba_config(void)
+{
+ /* Set up virtual channel 0 */
+ RCBA32(0x0014) = 0x80000001;
+ RCBA32(0x001c) = 0x03128010;
+
+/* Device 1f interrupt pin register */
+ RCBA32(0x3100) = 0x00042210;
+ /* Device 1d interrupt pin register */
+ RCBA32(0x310c) = 0x00214321;
+ /* HD Audio Interrupt */
+ RCBA32(0x3110) = 0x00000001;
+ /* dev irq route register */
+ RCBA16(0x3140) = 0x0132;
+ RCBA16(0x3142) = 0x0146;
+ RCBA16(0x3144) = 0x0237;
+ RCBA16(0x3146) = 0x3201;
+ RCBA16(0x3148) = 0x0146;
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) |= 3 << 24;
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
+ /* Enable PCIe Root Port Clock Gate */
+ RCBA32(0x341c) = 0x00000001;
+}
+
+static void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+ printk(BIOS_DEBUG, "program secondary mlt XXX byte\n");
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+ printk(BIOS_DEBUG, "reset rtc power status\n");
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ printk(BIOS_DEBUG, "usb transient disconnect\n");
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+ /*./inteltool -r on vendor bios*/
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ RCBA32(0x0214) = 0x10030549;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(0x3418) |= (1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+// RCBA32(0x3e0e) |= (1 << 7);
+// RCBA32(0x3e4e) |= (1 << 7);
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+
+
+}
+
+void main(unsigned long bist)
+{
+const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
+ int s3resume = 0;
+ device_t dev;
+
+ if (bist == 0)
+ enable_lapic();
+
+ ich7_enable_lpc();
+ /* Set up the console */
+// winbond_enable_serial(SERIAL_DEV,CONFIG_TTYS0_BASE);
+
+ dev = PNP_DEV(0x2e, W83627EHG_SP1);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
+ pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
+ pnp_set_enable(dev, 1);
+// SuperIO
+ dev = PNP_DEV(0x2e, W83627EHG_KBC); // Keyboard
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
+ pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
+ //pnp_write_config(dev, 0xf0, 0x82);
+ pnp_set_enable(dev, 1);
+
+ dev = PNP_DEV(0x2e, W83627EHG_GPIO2);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 1);
+
+ dev = PNP_DEV(0x2e, W83627EHG_GPIO3);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2
+ pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2
+ pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4
+
+ dev = PNP_DEV(0x2e, W83627EHG_FDC);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+
+ dev = PNP_DEV(0x2e, W83627EHG_PP);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+
+ /* Enable HWM */
+ dev = PNP_DEV(0x2e, W83627EHG_HWM);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
+ pnp_set_enable(dev, 1);
+
+ pnp_exit_ext_func_mode(dev);
+//
+ console_init();
+
+ report_bist_failure(bist);
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+ outb(0x6, 0xcf9);
+ halt();
+ }
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+
+// i945_early_initialization();
+
+ s3resume = southbridge_detect_s3_resume();
+
+ printk(BIOS_DEBUG, "Enable SPD ROMs and DDR-II DRAM\n");
+
+ enable_smbus();
+ x4x_early_init();
+
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+ dump_spd_registers();
+#endif
+ sdram_initialize(0, spd_addrmap);
+ quick_ram_check();
+ cbmem_initialize_empty();
+ printk(BIOS_DEBUG, "Memory initialized\n");
+
+ printk(BIOS_DEBUG, "Perform some initialization that must run before stage2\n");
+ early_ich7_init();
+
+ rcba_config();
+// printk(BIOS_DEBUG, "Chipset Errata!\n");
+// fixup_i945_errata(); this is probably not for desktop version.
+// i945_late_initialization(s3resume);
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c
new file mode 100644
index 0000000..760dda2
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.c
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <pc80/mc146818rtc.h>
+
+#include "superio_hwm.h"
+
+/* Hardware Monitor */
+
+#define FAN_CRUISE_CONTROL_DISABLED 0
+#define FAN_CRUISE_CONTROL_SPEED 1
+#define FAN_CRUISE_CONTROL_THERMAL 2
+
+#define FAN_SPEED_5625 0
+//#define FAN_TEMPERATURE_30DEGC 0
+
+#define HWM_BASE 0x290
+
+static void hwm_write(u8 reg, u8 value)
+{
+ outb(reg, HWM_BASE + 0x05);
+ outb(value, HWM_BASE + 0x06);
+}
+
+static void hwm_bank(u8 bank)
+{
+ hwm_write(0x4e, bank);
+}
+
+struct fan_speed {
+ u8 fan_in;
+ u16 fan_speed;
+};
+
+// FANIN Target Speed Register
+// FANIN = 337500 / RPM
+struct fan_speed fan_speeds[] = {
+ { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
+ { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
+ { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
+ { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
+};
+
+struct temperature {
+ u8 deg_celsius;
+ u8 deg_fahrenheit;
+};
+
+struct temperature temperatures[] = {
+ { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
+ { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
+ { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
+ { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
+};
+
+void hwm_setup(void)
+{
+ int cpufan_control = 0, sysfan_control = 0;
+ int cpufan_speed = 0, sysfan_speed = 0;
+ int cpufan_temperature = 0, sysfan_temperature = 0;
+
+ cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
+ get_option(&cpufan_control, "cpufan_cruise_control");
+ cpufan_speed = FAN_SPEED_5625;
+ get_option(&cpufan_speed, "cpufan_speed");
+ //cpufan_temperature = FAN_TEMPERATURE_30DEGC;
+ //get_option(&cpufan_temperature, "cpufan_temperature");
+
+ sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
+ get_option(&sysfan_control, "sysfan_cruise_control");
+ sysfan_speed = FAN_SPEED_5625;
+ get_option(&sysfan_speed, "sysfan_speed");
+ //sysfan_temperature = FAN_TEMPERATURE_30DEGC;
+ //get_option(&sysfan_temperature, "sysfan_temperature");
+
+ // hwm_write(0x31, 0x20); // AVCC high limit
+ // hwm_write(0x34, 0x06); // VIN2 low limit
+
+ hwm_bank(0);
+ hwm_write(0x59, 0x20); // Diode Selection
+ hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
+
+ hwm_bank(4);
+ hwm_write(0x54, 0xf1); // SYSTIN temperature offset
+ hwm_write(0x55, 0x19); // CPUTIN temperature offset
+ hwm_write(0x56, 0xfc); // AUXTIN temperature offset
+
+ hwm_bank(0x80); // Default
+
+ u8 fan_config = 0;
+ // 00 FANOUT is Manual Mode
+ // 01 FANOUT is Thermal Cruise Mode
+ // 10 FANOUT is Fan Speed Cruise Mode
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ fan_config |= (2 << 4);
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ fan_config |= (1 << 4);
+ break;
+ }
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ fan_config |= (2 << 2);
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ fan_config |= (1 << 2);
+ break;
+ }
+ // This register must be written first
+ hwm_write(0x04, fan_config);
+
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG,
+ "Fan Cruise Control setting CPU fan to %d RPM\n",
+ fan_speeds[cpufan_speed].fan_speed);
+ hwm_write(0x06,
+ fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG,
+ "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
+ temperatures[cpufan_temperature].deg_celsius,
+ temperatures[cpufan_temperature].deg_fahrenheit);
+ hwm_write(0x06,
+ temperatures[cpufan_temperature].deg_celsius);
+ // CPUFANIN target temperature
+ break;
+ }
+
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG,
+ "Fan Cruise Control setting system fan to %d RPM\n",
+ fan_speeds[sysfan_speed].fan_speed);
+ hwm_write(0x05,
+ fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG,
+ "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
+ temperatures[sysfan_temperature].deg_celsius,
+ temperatures[sysfan_temperature].deg_fahrenheit);
+ hwm_write(0x05,
+ temperatures[sysfan_temperature].deg_celsius);
+ // SYSFANIN target temperature
+ break;
+ }
+
+ hwm_write(0x0e, 0x02); // Fan Output Step Down Time
+ hwm_write(0x0f, 0x02); // Fan Output Step Up Time
+
+ hwm_write(0x47, 0xaf); // FAN divisor register
+ hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
+
+ hwm_write(0x40, 0x01); // Init, but no SMI#
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h
new file mode 100644
index 0000000..f552c30
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_HWM_H
+#define SUPERIO_HWM_H
+
+void hwm_setup(void);
+
+#endif /* SUPERIO_HWM_H */
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