[coreboot-gerrit] Patch set updated for coreboot: soc/intel/common: Implement common cpu functions

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14385

-gerrit

commit 632a33966904cd689703ab0bfd2b67d8ab98869c
Author: Hannah Williams <hannah.williams at intel.com>
Date:   Fri Apr 15 11:51:50 2016 -0700

    soc/intel/common: Implement common cpu functions
    
    Change-Id: I4422e752c5c77eb8e1f627711ad54e98430407b2
    Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
 src/soc/intel/common/Makefile.inc |  1 +
 src/soc/intel/common/cpu.c        | 38 ++++++++++++++++++++++++++++++++++++++
 src/soc/intel/common/cpu.h        | 23 +++++++++++++++++++++++
 3 files changed, 62 insertions(+)

diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index a7218b7..7de13e3 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -14,6 +14,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 ramstage-y += util.c
 ramstage-$(CONFIG_MMA) += mma.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
+ramstage-$(CONFIG_CPU_COMMON) += cpu.c
 
 # Create and add the MRC cache to the cbfs image
 ifneq ($(CONFIG_CHROMEOS),y)
diff --git a/src/soc/intel/common/cpu.c b/src/soc/intel/common/cpu.c
new file mode 100644
index 0000000..4c5ce2c
--- /dev/null
+++ b/src/soc/intel/common/cpu.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <soc/cpu.h>
+#include "cpu.h"
+
+void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
+{
+        msr_t msr;
+        msr = rdmsr(MSR_CORE_THREAD_COUNT);
+        *num_virt = (msr.lo >> 0) & 0xffff;
+        *num_phys = (msr.lo >> 16) & 0xffff;
+}
+
+void enable_lapic_tpr(void)
+{
+        msr_t msr;
+
+        msr = rdmsr(MSR_PIC_MSG_CONTROL);
+        msr.lo &= ~(1 << 10);   /* Enable APIC TPR updates */
+        wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
diff --git a/src/soc/intel/common/cpu.h b/src/soc/intel/common/cpu.h
new file mode 100644
index 0000000..eba4433
--- /dev/null
+++ b/src/soc/intel/common/cpu.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _SOC_COMMON_CPU_H_
+#define _SOC_COMMON_CPU_H_
+
+void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt);
+void enable_lapic_tpr(void);
+
+#endif