[coreboot-gerrit] New patch to review for coreboot: intel/amenia: configure interrupt trigger mode

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14353

-gerrit

commit 5f86c11097c7dfff7083cf770e2f4b0952c3aef7
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date:   Fri Mar 4 14:00:04 2016 -0800

    intel/amenia: configure interrupt trigger mode
    
    Provide trigger option to configure APIC, sci, smi, nmi interrupts.
    
    Change-Id: I1b553fb4ed1b43aba62346f5b758f8d082606510
    Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
    Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
 src/soc/intel/apollolake/include/soc/gpio.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index 8f78de2..f64d6c7 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -48,28 +48,28 @@
 		PAD_PULL(pull))
 
 /* General purpose input, routed to APIC */
-#define PAD_CFG_GPI_APIC(pad, pull, rst) \
+#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull))
+		PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull))
 
 /* General purpose input, routed to SMI */
-#define PAD_CFG_GPI_SMI(pad, pull, rst, inv) \
+#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(SMI, LEVEL, inv), PAD_PULL(pull))
+		PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull))
 
 /* General purpose input, routed to SCI */
-#define PAD_CFG_GPI_SCI(pad, pull, rst, inv) \
+#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(SCI, LEVEL, inv), PAD_PULL(pull))
+		PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull))
 
 /* General purpose input, routed to NMI */
-#define PAD_CFG_GPI_NMI(pad, pull, rst, inv) \
+#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
 	_PAD_CFG_STRUCT(pad,		\
 		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(NMI, LEVEL, inv), PAD_PULL(pull))
+		PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull))
 
 struct pad_config {
 	uint32_t config0;