[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add tsc_freq.c to all the stages

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14339

-gerrit

commit 8387ecb66d135e3932eaa18fd564624c465591a1
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Tue Apr 12 17:00:52 2016 -0700

    soc/intel/apollolake: Add tsc_freq.c to all the stages
    
    Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/Makefile.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 328a5b4..3e307f5 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -25,6 +25,7 @@ romstage-y += gpio.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 romstage-y += memmap.c
 romstage-y += mmap_boot.c
+romstage-y += tsc_freq.c
 
 smm-y += placeholders.c
 
@@ -40,6 +41,7 @@ ramstage-y += mmap_boot.c
 ramstage-y += uart.c
 ramstage-y += northbridge.c
 ramstage-y += spi.c
+ramstage-y += tsc_freq.c
 
 postcar-y += exit_car.S
 postcar-y += memmap.c