[coreboot-gerrit] New patch to review for coreboot: rockchip/rk3288: refactor pwm driver
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Apr 12 16:04:36 CEST 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14336
-gerrit
commit 3dd5d144562476e4464094de5705cf73de7998c9
Author: Lin Huang <hl at rock-chips.com>
Date: Wed Mar 23 19:35:46 2016 +0800
rockchip/rk3288: refactor pwm driver
3288 and 3399 use the same pwm controller.
With this patch in place it is easy to add support for 3399.
BRANCH=none
BUG=none
TEST=booted veyron_jerry to kernel login prompt
Change-Id: If8f5697b4003d078b46de3fa3cebad6c8310a688
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: acf6132619167743c0c991b75f0f49c8d0e51ca7
Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Change-Id: I79428f9ec71017ad8f3ad67dac1468178ccc3a1e
Original-Reviewed-on: https://chromium-review.googlesource.com/338019
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/soc/rockchip/common/pwm.c | 86 ++++++++++++++++++++++++
src/soc/rockchip/rk3288/Makefile.inc | 4 +-
src/soc/rockchip/rk3288/include/soc/addressmap.h | 2 +-
src/soc/rockchip/rk3288/include/soc/clock.h | 2 +
src/soc/rockchip/rk3288/pwm.c | 84 -----------------------
5 files changed, 91 insertions(+), 87 deletions(-)
diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c
new file mode 100644
index 0000000..c294a0c
--- /dev/null
+++ b/src/soc/rockchip/common/pwm.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/grf.h>
+#include <soc/soc.h>
+#include <soc/pwm.h>
+#include <soc/clock.h>
+#include <stdlib.h>
+#include <timer.h>
+
+struct pwm_ctl {
+ u32 pwm_cnt;
+ u32 pwm_period_hpr;
+ u32 pwm_duty_lpr;
+ u32 pwm_ctrl;
+};
+
+struct rk_pwm_regs {
+ struct pwm_ctl pwm[4];
+ u32 intsts;
+ u32 int_en;
+};
+check_member(rk_pwm_regs, int_en, 0x44);
+
+#define RK_PWM_DISABLE (0 << 0)
+#define RK_PWM_ENABLE (1 << 0)
+
+
+#define PWM_ONE_SHOT (0 << 1)
+#define PWM_CONTINUOUS (1 << 1)
+#define RK_PWM_CAPTURE (1 << 2)
+
+#define PWM_DUTY_POSTIVE (1 << 3)
+#define PWM_DUTY_NEGATIVE (0 << 3)
+
+#define PWM_INACTIVE_POSTIVE (1 << 4)
+#define PWM_INACTIVE_NEGATIVE (0 << 4)
+
+#define PWM_OUTPUT_LEFT (0 << 5)
+#define PWM_OUTPUT_CENTER (1 << 5)
+
+#define PWM_LP_ENABLE (1 << 8)
+#define PWM_LP_DISABLE (0 << 8)
+
+#define PWM_SEL_SCALE_CLK (1 << 9)
+#define PWM_SEL_SRC_CLK (0 << 9)
+
+struct rk_pwm_regs *rk_pwm = (void *)RK_PWM_BASE;
+
+void pwm_init(u32 id, u32 period_ns, u32 duty_ns)
+{
+ unsigned long period, duty;
+
+#if IS_ENABLED(CONFIG_SOC_ROCKCHIP_RK3288)
+ /*use rk pwm*/
+ write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0));
+#endif
+
+ write32(&rk_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK |
+ PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS |
+ PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE);
+
+ period = (PWM_CLOCK_HZ / 1000) * period_ns / USECS_PER_SEC;
+ duty = (PWM_CLOCK_HZ / 1000) * duty_ns / USECS_PER_SEC;
+
+ write32(&rk_pwm->pwm[id].pwm_period_hpr, period);
+ write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty);
+ setbits_le32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
+}
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index a57ead3..553bd00 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -49,7 +49,7 @@ romstage-y += gpio.c
romstage-y += ../common/spi.c
romstage-y += sdram.c
romstage-y += ../common/rk808.c
-romstage-y += pwm.c
+romstage-y += ../common/pwm.c
romstage-y += tsadc.c
ramstage-y += soc.c
@@ -62,7 +62,7 @@ ramstage-y += ../common/spi.c
ramstage-y += sdram.c
ramstage-y += gpio.c
ramstage-y += ../common/rk808.c
-ramstage-y += pwm.c
+ramstage-y += ../common/pwm.c
ramstage-y += vop.c
ramstage-y += edp.c
ramstage-y += hdmi.c
diff --git a/src/soc/rockchip/rk3288/include/soc/addressmap.h b/src/soc/rockchip/rk3288/include/soc/addressmap.h
index fb07caf..ba59404 100644
--- a/src/soc/rockchip/rk3288/include/soc/addressmap.h
+++ b/src/soc/rockchip/rk3288/include/soc/addressmap.h
@@ -52,7 +52,7 @@
#define I2C0_BASE 0xFF650000
#define I2C2_BASE 0xFF660000
#define DW_PWM0123_BASE 0xFF670000
-#define RK_PWM0123_BASE 0xFF680000
+#define RK_PWM_BASE 0xFF680000
#define UART2_BASE 0xFF690000
#define TIMER0_BASE 0xFF6B0000
diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h
index 9592c98..a629789 100644
--- a/src/soc/rockchip/rk3288/include/soc/clock.h
+++ b/src/soc/rockchip/rk3288/include/soc/clock.h
@@ -39,6 +39,8 @@ enum apll_frequencies {
#define PERI_HCLK_HZ (148500*KHz)
#define PERI_PCLK_HZ (74250*KHz)
+#define PWM_CLOCK_HZ PD_BUS_PCLK_HZ
+
void rkclk_init(void);
void rkclk_configure_spi(unsigned int bus, unsigned int hz);
void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
diff --git a/src/soc/rockchip/rk3288/pwm.c b/src/soc/rockchip/rk3288/pwm.c
deleted file mode 100644
index c609cb4..0000000
--- a/src/soc/rockchip/rk3288/pwm.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <console/console.h>
-#include <delay.h>
-#include <soc/addressmap.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pwm.h>
-#include <soc/clock.h>
-#include <stdlib.h>
-#include <timer.h>
-
-struct pwm_ctl {
- u32 pwm_cnt;
- u32 pwm_period_hpr;
- u32 pwm_duty_lpr;
- u32 pwm_ctrl;
-};
-
-struct rk3288_pwm_regs {
- struct pwm_ctl pwm[4];
- u32 intsts;
- u32 int_en;
-};
-check_member(rk3288_pwm_regs, int_en, 0x44);
-
-#define RK_PWM_DISABLE (0 << 0)
-#define RK_PWM_ENABLE (1 << 0)
-
-
-#define PWM_ONE_SHOT (0 << 1)
-#define PWM_CONTINUOUS (1 << 1)
-#define RK_PWM_CAPTURE (1 << 2)
-
-#define PWM_DUTY_POSTIVE (1 << 3)
-#define PWM_DUTY_NEGATIVE (0 << 3)
-
-#define PWM_INACTIVE_POSTIVE (1 << 4)
-#define PWM_INACTIVE_NEGATIVE (0 << 4)
-
-#define PWM_OUTPUT_LEFT (0 << 5)
-#define PWM_OUTPUT_CENTER (1 << 5)
-
-#define PWM_LP_ENABLE (1 << 8)
-#define PWM_LP_DISABLE (0 << 8)
-
-#define PWM_SEL_SCALE_CLK (1 << 9)
-#define PWM_SEL_SRC_CLK (0 << 9)
-
-struct rk3288_pwm_regs *rk3288_pwm = (void *)RK_PWM0123_BASE;
-
-void pwm_init(u32 id, u32 period_ns, u32 duty_ns)
-{
- unsigned long period, duty;
-
- /*use rk pwm*/
- write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0));
-
- write32(&rk3288_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK |
- PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS |
- PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE);
-
- period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC;
- duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC;
-
- write32(&rk3288_pwm->pwm[id].pwm_period_hpr, period);
- write32(&rk3288_pwm->pwm[id].pwm_duty_lpr, duty);
- setbits_le32(&rk3288_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
-}
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