[coreboot-gerrit] Patch set updated for coreboot: sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Mon Apr 11 17:50:19 CEST 2016
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14307
-gerrit
commit adb53c26a5f2de9d946285bd3f86dc58bfc1a911
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Sun Apr 10 15:52:47 2016 -0500
sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02
Change-Id: Ifb568ca126283e533232f52175d6147ee500220c
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/southbridge/amd/sb700/early_setup.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 32234e2..aae845f 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -403,7 +403,7 @@ static void sb700_devices_por_init(void)
printk(BIOS_INFO, "%s: Secondary SMBUS controller I/O not found\n", __func__);
}
else {
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100))
+ if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) {
/* Disable legacy sensor support / reset ASF Slave state machine per RPR 2.27 step 3 */
outb(0x40, SMBUS_AUX_IO_BASE + SMBSLVMISC);
}
@@ -677,6 +677,11 @@ static void sb700_pmio_por_init(void)
pmio_write(0xbb, byte);
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+ /* RPR 2.26 Alter CPU reset timing */
+ byte = pmio_read(0xb2);
+ byte |= 0x1 << 2; /* Enable CPU reset timing option */
+ pmio_write(0xb2, byte);
+
/* Work around system clock drift issues */
byte = pmio_read(0xd4);
byte |= 0x1 << 6; /* Enable alternate 14MHz clock source */
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