[coreboot-gerrit] Patch set updated for coreboot: sb/amd/sp5100: Apply Sx State Settings per RPR v3.02

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14308

-gerrit

commit 249c7338b19a7de62f2cccd84c9f181762ea737b
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Sun Apr 10 16:02:42 2016 -0500

    sb/amd/sp5100: Apply Sx State Settings per RPR v3.02
    
    Change-Id: Iacf84ac7de4362e523ad9d8aa7309eecd5277480
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sb700/early_setup.c | 64 +++++++++++++++++++--------------
 1 file changed, 37 insertions(+), 27 deletions(-)

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 24fbb91..dc2daa9 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -606,40 +606,50 @@ static void sb700_pmio_por_init(void)
 	byte |= 0x20;
 	pmio_write(0x66, byte);
 
-	/* RPR2.31 PM_TURN_OFF_MSG during ASF Shutdown. */
-	if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12) {
+	if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) {
+		/* RPR 2.11 Sx State Settings */
 		byte = pmio_read(0x65);
-		byte &= ~(1 << 7);
+		byte &= ~(1 << 7);		/* SpecialFunc = 0 */
 		pmio_write(0x65, byte);
 
-		byte = pmio_read(0x75);
-		byte &= 0xc0;
-		byte |= 0x05;
-		pmio_write(0x75, byte);
-
-		byte = pmio_read(0x52);
-		byte &= 0xc0;
-		byte |= 0x08;
-		pmio_write(0x52, byte);
+		byte = pmio_read(0x68);
+		byte |= 1 << 2;			/* MaskApicEn = 1 */
+		pmio_write(0x68, byte);
 	} else {
-		byte = pmio_read(0xD7);
-		byte |= 1 << 0;
-		pmio_write(0xD7, byte);
-
-		byte = pmio_read(0x65);
-		byte |= 1 << 7;
-		pmio_write(0x65, byte);
+		/* RPR2.31 PM_TURN_OFF_MSG during ASF Shutdown. */
+		if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12) {
+			byte = pmio_read(0x65);
+			byte &= ~(1 << 7);
+			pmio_write(0x65, byte);
+
+			byte = pmio_read(0x75);
+			byte &= 0xc0;
+			byte |= 0x05;
+			pmio_write(0x75, byte);
+
+			byte = pmio_read(0x52);
+			byte &= 0xc0;
+			byte |= 0x08;
+			pmio_write(0x52, byte);
+		} else {
+			byte = pmio_read(0xD7);
+			byte |= 1 << 0;
+			pmio_write(0xD7, byte);
 
-		byte = pmio_read(0x75);
-		byte &= 0xc0;
-		byte |= 0x01;
-		pmio_write(0x75, byte);
+			byte = pmio_read(0x65);
+			byte |= 1 << 7;
+			pmio_write(0x65, byte);
 
-		byte = pmio_read(0x52);
-		byte &= 0xc0;
-		byte |= 0x02;
-		pmio_write(0x52, byte);
+			byte = pmio_read(0x75);
+			byte &= 0xc0;
+			byte |= 0x01;
+			pmio_write(0x75, byte);
 
+			byte = pmio_read(0x52);
+			byte &= 0xc0;
+			byte |= 0x02;
+			pmio_write(0x52, byte);
+		}
 	}
 
 	/* Watch Dog Timer Control