[coreboot-gerrit] New patch to review for coreboot: sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14307

-gerrit

commit 47874ccdac9a12ef60f9e70606c9ccb80a26a6de
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Sun Apr 10 15:52:47 2016 -0500

    sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02
    
    Change-Id: Ifb568ca126283e533232f52175d6147ee500220c
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sb700/early_setup.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 3333841..24fbb91 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -676,6 +676,11 @@ static void sb700_pmio_por_init(void)
 	pmio_write(0xbb, byte);
 
 #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+	/* RPR 2.26 Alter CPU reset timing */
+	byte = pmio_read(0xb2);
+	byte |= 0x1 << 2;	/* Enable CPU reset timing option */
+	pmio_write(0xb2, byte);
+
 	/* Work around system clock drift issues */
 	byte = pmio_read(0xd4);
 	byte |= 0x1 << 6;	/* Enable alternate 14MHz clock source */