[coreboot-gerrit] New patch to review for coreboot: sb/amd/sp5100: Disable SPI prefetch to stabilize boot

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14304

-gerrit

commit 64e82ce80d01c7dd404ecc2e559c60e5e8ab4387
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Sat Apr 9 20:57:02 2016 -0500

    sb/amd/sp5100: Disable SPI prefetch to stabilize boot
    
    The SP5100 series devices contain a very poorly documented hardware
    bug, possibly related to erratum 18 and/or erratum 20, which causes
    a deadlock on boot requiring removal and reapplication of AC power.
    
    It has been determined experimentally that for affected systems
    disabling SPI prefetch greatly reduces the chances of the bug
    appearing.
    
    Change-Id: I616194bc8f011b4dbdf1ad3688cf759662c6f688
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sb700/early_setup.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index ffdd34b..da4090a 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -176,9 +176,19 @@ void sb7xx_51xx_lpc_init(void)
 	reg8 |= (1 << 5) | (1 << 6);
 	pci_write_config8(dev, 0x47, reg8);
 
-	/* Enable PrefetchEnSPIFromHost to speed up SPI flash read (does not affect LPC) */
 	reg8 = pci_read_config8(dev, 0xbb);
-	reg8 |= 1 << 0;
+	if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)) {
+		/* PrefetchEnSPIFromHost causes significant problems on SP5100 devices,
+		 * including increasing the probability of hard deadlock requiring power
+		 * removal / reapplication.
+		 * Disable it on SP5100 devices.
+		 */
+		reg8 &= ~(1 << 0);
+	}
+	else {
+		/* Enable PrefetchEnSPIFromHost to speed up SPI flash read (does not affect LPC) */
+		reg8 |= 1 << 0;
+	}
 	pci_write_config8(dev, 0xbb, reg8);
 
 	/* Super I/O, RTC */