[coreboot-gerrit] Patch set updated for coreboot: cpu/x86/tsc: remove conditional compilation

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14302

-gerrit

commit 8266c69a6b9533f86732871b1fff867b8a5cd96d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Apr 8 21:41:01 2016 -0500

    cpu/x86/tsc: remove conditional compilation
    
    The delay_tsc.c compilation unit used the C preprocessor
    to conditionally compile different code paths. Instead of
    guarding large blocks of code allow the compiler to optimize
    out unreachable code.
    
    Change-Id: I660c21d6f4099b0d7aefa84b14f1e68d6fd732c3
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/cpu/x86/tsc/delay_tsc.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index 439b477..6120b88 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -9,12 +9,6 @@
 
 static unsigned long clocks_per_usec CAR_GLOBAL;
 
-#if CONFIG_TSC_CONSTANT_RATE
-static unsigned long calibrate_tsc(void)
-{
-	return tsc_freq_mhz();
-}
-#else /* CONFIG_TSC_CONSTANT_RATE */
 #define CLOCK_TICK_RATE	1193180U /* Underlying HZ */
 
 /* ------ Calibrate the TSC -------
@@ -28,7 +22,7 @@ static unsigned long calibrate_tsc(void)
 #define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */
 #define CALIBRATE_DIVISOR  (2*1000) /* 2ms / 2000 == 1usec */
 
-static unsigned long long calibrate_tsc(void)
+static unsigned long calibrate_tsc_with_pit(void)
 {
 	/* Set the Gate high, disable speaker */
 	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
@@ -89,7 +83,13 @@ bad_ctc:
 	return 0;
 }
 
-#endif /* CONFIG_TSC_CONSTANT_RATE */
+static unsigned long calibrate_tsc(void)
+{
+	if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+		return tsc_freq_mhz();
+	else
+		return calibrate_tsc_with_pit();
+}
 
 void init_timer(void)
 {