[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Enable CACHE_MRC_SETTINGS
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Sat Apr 9 00:33:28 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14252
-gerrit
commit 87b23b0b7a6e7477099aef78f372c52c32a3f249
Author: Hannah Williams <hannah.williams at intel.com>
Date: Mon Mar 14 17:38:51 2016 -0700
soc/intel/apollolake: Enable CACHE_MRC_SETTINGS
This enables CACHE_MRC_SETTINGS by default as well selects
timer configuration.
Change-Id: I0248001892ef763c39097848b5adc8c1befed1f0
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/Kconfig | 8 ++++++--
src/soc/intel/apollolake/Makefile.inc | 1 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 30ee7e5..10e8b0d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -35,8 +35,8 @@ config CPU_SPECIFIC_OPTIONS
select SPI_FLASH
select UDELAY_TSC
select TSC_CONSTANT_RATE
- select UDELAY_TSC
- select TSC_CONSTANT_RATE
+ select TSC_MONOTONIC_TIMER
+ select HAVE_MONOTONIC_TIMER
select PLATFORM_USES_FSP2_0
config MMCONF_BASE_ADDRESS
@@ -100,4 +100,8 @@ config ROMSTAGE_ADDR
help
The base address (in CAR) where romstage should be linked
+config CACHE_MRC_SETTINGS
+ bool
+ default y
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index eb3058d..dff1589 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -44,6 +44,7 @@ postcar-y += exit_car.S
postcar-y += memmap.c
postcar-y += mmap_boot.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+postcar-y += tsc_freq.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
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