[coreboot-gerrit] New patch to review for coreboot: cpu/x86/tsc: Compile TSC timer for postcar as well.
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Fri Apr 8 23:49:50 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14298
-gerrit
commit d2607a3f83c5eb699e10352f7181186abac33f34
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Fri Apr 8 14:31:54 2016 -0700
cpu/x86/tsc: Compile TSC timer for postcar as well.
Change-Id: I8fd79d438756aae03649e320d4d640cee284d88a
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/cpu/x86/tsc/Makefile.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc
index 7e2eab2..9751cac 100644
--- a/src/cpu/x86/tsc/Makefile.inc
+++ b/src/cpu/x86/tsc/Makefile.inc
@@ -2,6 +2,7 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c
ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
+postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
endif
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