[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Add boot mode constants

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14249

-gerrit

commit a7272595fd09128fc1e0f24cca4c8a95174ce02c
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Thu Mar 17 16:42:41 2016 -0700

    drivers/intel/fsp2_0: Add boot mode constants
    
    This adds boot mode constants. They match EDK2 found in PiBootMode.h
    constants but are part of FSP2.0 spec.
    
    Change-Id: I16ee90ff372d252ddc042ca89c1e5912ab041616
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/drivers/intel/fsp2_0/include/fsp/api.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index c098a5b..d49fc42 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -35,6 +35,16 @@ enum fsp_status {
 	FSP_CRC_ERROR = 0x8000001b,
 };
 
+enum fsp_boot_mode {
+	FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00,
+	FSP_BOOT_WITH_MINIMAL_CONFIGURATION = 0x01,
+	FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES = 0x02,
+	FSP_BOOT_ON_S4_RESUME = 0x05,
+	FSP_BOOT_ON_S3_RESUME = 0x11,
+	FSP_BOOT_ON_FLASH_UPDATE = 0x12,
+	FSP_BOOT_IN_RECOVERY_MODE = 0x20
+};
+
 enum fsp_notify_phase {
 	AFTER_PCI_ENUM = 0x20,
 	READY_TO_BOOT = 0x40