[coreboot-gerrit] New patch to review for coreboot: [WIP] riscv: change some files to make it build in newer toolchain

[Iru Cai (mytbk920423@gmail.com)]

Iru Cai (mytbk920423 at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14274

-gerrit

commit 1ec35904b49769163ad558cf2beb11c94f1dfcbf
Author: Iru Cai <mytbk920423 at gmail.com>
Date:   Thu Apr 7 15:49:35 2016 +0800

    [WIP] riscv: change some files to make it build in newer toolchain
    
    src/arch/riscv/bootblock.S: change `la' with immediate operand to `li'
    src/arch/riscv/trap_util.S: change `la' with immediate operand to `li'
    
    Still cannot build due to binutils issues:
        CC         bootblock/mainboard/emulation/spike-riscv/spike_util.o
        src/mainboard/emulation/spike-riscv/spike_util.c: Assembler messages:
        src/mainboard/emulation/spike-riscv/spike_util.c:63: Error: Instruction csrw requires absolute expression
    
    Signed-off-by: Iru Cai <mytbk920423 at gmail.com>
    Change-Id: I556ca8c45eba81495e0312f8f92a2de11b0a77af
---
 src/arch/riscv/bootblock.S | 4 ++--
 src/arch/riscv/trap_util.S | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 27c80eb..029e9e4 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -35,7 +35,7 @@ machine_handler:
 _start:
 
 	// pending figuring out this f-ing toolchain. Hardcode what we know works.
-  la sp, 0x80FFF0 // stack start + stack size
+  li sp, 0x80FFF0 // stack start + stack size
 
   # make room for HLS and initialize it
   addi sp, sp, -64 // MENTRY_FRAME_SIZE
@@ -43,7 +43,7 @@ _start:
   call hls_init
 
   //poison the stack
-  la t1, 0x800000
+  li t1, 0x800000
   li t0, 0xdeadbeef
   sd t0, 0(t1)
 
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index bc09dc9..0118ffc 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -108,7 +108,7 @@
 supervisor_trap_entry:
     csrw mscratch, sp
     # load in the top of the machine stack
-    la sp, 0x80FFF0 - 64
+    li sp, 0x80FFF0 - 64
     1:addi sp,sp,-320
     save_tf
     move  a0,sp