[coreboot-gerrit] Patch set updated for coreboot: sb/amd/sb700: Enable reset on sync flood

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14260

-gerrit

commit cd7101035d2af4e8e35d944d3a1e78e9f0ee7d23
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Tue Apr 5 23:10:48 2016 -0500

    sb/amd/sb700: Enable reset on sync flood
    
    The logic to enable reset on sync flood per RPR guidelines
    somehow ended up guarded on the SATA AHCI setup.  Unconditionally
    enable reset on sync flood per the RPR.
    
    Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sb700/early_setup.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 76855fb..8042849 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -543,13 +543,13 @@ static void sb700_devices_por_init(void)
 
 			/* set Device ID consistent with IDE emulation mode configuration */
 			pci_write_config32(dev, 0x0, 0x43901002);
-
-			/* rpr v2.13 4.17 Reset CPU on Sync Flood */
-			abcfg_reg(0x10050, 1 << 2, 1 << 2);
 		}
 #endif
 	}
 
+	/* rpr v2.13 4.17 Reset CPU on Sync Flood */
+	abcfg_reg(0x10050, 1 << 2, 1 << 2);
+
 	/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
 	printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-17-0\n");
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);