[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add lpc device driver
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Tue Apr 5 02:23:06 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13356
-gerrit
commit 68a78f55b263f2e303b739dac58f3a00ec0d3e54
Author: Lance Zhao <lijian.zhao at intel.com>
Date: Thu Nov 12 18:19:41 2015 -0800
soc/apollolake: Add lpc device driver
A dedicated pci device driver required for LPC devices as the legacy IO range
need to be included to avoid IO resource confilict. Blindly set to 0~0x1000 to
also avoid the IO resource of COMA/COMB/LPT/FDD and LPC.Without this driver
system will have assertion on load RTC DXE driver in UEFI payloads.
Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35
Signed-off-by: Lance Zhao <lijian.zhao at intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 1 +
src/soc/intel/apollolake/lpc.c | 48 +++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 70ab515..98db608 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -34,6 +34,7 @@ ramstage-y += chip.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += mmap_boot.c
ramstage-y += uart.c
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
new file mode 100644
index 0000000..80e693c
--- /dev/null
+++ b/src/soc/intel/apollolake/lpc.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_ids.h>
+
+static void soc_lpc_add_io_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Add the default claimed legacy IO range for the LPC device. */
+ res = new_resource(dev, 0);
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void soc_lpc_read_resources(device_t dev)
+{
+ /* Get the PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add IO resources to LPC. */
+ soc_lpc_add_io_resources(dev);
+}
+
+static struct device_operations device_ops = {
+ .read_resources = &soc_lpc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+};
+
+static const struct pci_driver soc_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = PCI_DEVICE_ID_APOLLOLAKE_LPC,
+};
More information about the coreboot-gerrit
mailing list