[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Fill _PRT entry in DSDT
Lijian Zhao (lijian.zhao@intel.com)
gerrit at coreboot.org
Tue Apr 5 00:19:26 CEST 2016
Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14243
-gerrit
commit 624b5a38c6c1ac64155e7090b4de7ae776b20837
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date: Wed Dec 2 15:34:45 2015 -0800
soc/intel/apollolake: Fill _PRT entry in DSDT
ACPI aware OS will need _PRT table to get desired interrupt
resource assigned and make device driver working. The logical
device within SOC gets fixed interrupt line.
Change-Id: I75141bd62ca2594b74983dff54912e0b20458b9a
Signed-off-by: Zhao, Lijian <lijian.zhao at intel.com>
---
src/soc/intel/apollolake/acpi/pci_irqs.asl | 53 ++++++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/soc_int.asl | 43 ++++++++++++++++++++++++
2 files changed, 96 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl
new file mode 100644
index 0000000..a378eee
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "soc_int.asl"
+
+Method(_PRT)
+{
+ Return(Package() {
+
+ Package(){0x0000FFFF, 0, 0, NPK_INT}, /* NPK */
+ Package(){0x0000FFFF, 1, 0, PUNIT_INT}, /* Punit(DPTF) */
+ Package(){0x0002FFFF, 0, 0, GEN_INT}, /* Gen */
+ Package(){0x0003FFFF, 0, 0, IUNIT_INT}, /* Iunit */
+ Package(){0x000DFFFF, 1, 0, PMC_INT}, /* PMC */
+ Package(){0x000EFFFF, 0, 0, AUDIO_INT}, /* Audio */
+ Package(){0x000FFFFF, 0, 0, CSE_INT}, /* CSE */
+ Package(){0x0011FFFF, 0, 0, ISH_INT}, /* ISH */
+ Package(){0x0012FFFF, 0, 0, SATA_INT}, /* SATA */
+ Package(){0x0013FFFF, 0, 0, PCIEA_INT}, /* PCIe-A 0 */
+ Package(){0x0014FFFF, 0, 0, PCIB_INT}, /* PCIe-B 0 */
+ Package(){0x0015FFFF, 0, 0, XHCI_INT}, /* xHCI */
+ Package(){0x0015FFFF, 1, 0, XDCI_INT}, /* xDCI */
+ Package(){0x0016FFFF, 0, 0, I2C0_INT}, /* I2C0 */
+ Package(){0x0016FFFF, 1, 0, I2C1_INT}, /* I2C1 */
+ Package(){0x0016FFFF, 2, 0, I2C2_INT}, /* I2C2 */
+ Package(){0x0016FFFF, 3, 0, I2C3_INT}, /* I2C3 */
+ Package(){0x0017FFFF, 0, 0, I2C4_INT}, /* I2C4 */
+ Package(){0x0017FFFF, 1, 0, I2C5_INT}, /* I2C5 */
+ Package(){0x0017FFFF, 2, 0, I2C6_INT}, /* I2C6 */
+ Package(){0x0017FFFF, 3, 0, I2C7_INT}, /* I2C7 */
+ Package(){0x0018FFFF, 0, 0, UART0_INT}, /* UART0 */
+ Package(){0x0018FFFF, 1, 0, UART1_INT}, /* UART1 */
+ Package(){0x0018FFFF, 2, 0, UART2_INT}, /* UART2 */
+ Package(){0x0018FFFF, 3, 0, UART3_INT}, /* UART3 */
+ Package(){0x0019FFFF, 0, 0, SPI0_INT}, /* SPI0 */
+ Package(){0x0019FFFF, 1, 0, SPI1_INT}, /* SPI1 */
+ Package(){0x0019FFFF, 2, 0, SPI2_INT}, /* SPI2 */
+ Package(){0x001BFFFF, 0, 0, SDCARD_INT}, /* SDCard */
+ Package(){0x001CFFFF, 0, 0, EMMC_INT}, /* eMMC */
+ Package(){0x001EFFFF, 0, 0, SDIO_INT}, /* SDIO */
+ Package(){0x001FFFFF, 1, 0, SMBUS_INT}, /* SMBUS */
+ }
+ )
+}
diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl
new file mode 100644
index 0000000..a49341c
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/soc_int.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_INT_DEFINE_ASL_
+#define _SOC_INT_DEFINE_ASL_
+
+#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/
+#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/
+#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/
+#define UART1_INT 6 /* Need to be shared by PMC and SCC only*/
+#define UART1_INT 7 /* Need to be shared by PMC and SCC only*/
+#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/
+#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/
+#define SMBUS_INT 20 /* PIRQE */
+#define PUNIT_INT 24
+#define AUDIO_INT 25
+#define ISH_INT 26
+#define I2C0_INT 27
+#define I2C1_INT 28
+#define I2C2_INT 29
+#define I2C3_INT 30
+#define I2C4_INT 31
+#define I2C5_INT 32
+#define I2C6_INT 33
+#define I2C7_INT 34
+#define SPI0_INT 35
+#define SPI1_INT 36
+#define SPI2_INT 37
+#define UFS_INT 38
+#define EMMC_INT 39
+#define SDIO_INT 42
+
+
+#endif /* _SOC_INT_DEFINE_ASL_ */
\ No newline at end of file
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