[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: use CAR code coherency for all CAR stages

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 595688a3d60c7ad0227ec7f72d8f2e73fd8f236e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Mar 31 11:38:13 2016 -0500

    soc/intel/apollolake: use CAR code coherency for all CAR stages
    
    The flush L1D to L2 operation was only being used when loading
    romstage from bootblock. However, when the FSP-M component is
    loaded no code coherency actions are taken. I suspect this is
    because the FSP-M component is larger than the 24KiB L1D and
    the entry point is early in the image. Thus, when loading
    the FSP-M component the earlier part of the image is flushed
    out to L2 in the process of loading the latter part of the
    component. Also, once verstage is introduced the same
    code coherency actions need to be taken as well. Therefore,
    position the apollolake code to handle all these cases.
    
    Change-Id: Ie71764f1b420a6072c4f149ad3e37278b6cb70e1
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/14210
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan at google.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>


See https://review.coreboot.org/14210 for details.

-gerrit