[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add lpss dsdt entry

[Lijian Zhao (lijian.zhao@intel.com)]

Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14218

-gerrit

commit 86d6c5c02b07c3d3c24cb2a6c83183edd9985cfd
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date:   Wed Jan 20 13:02:38 2016 -0800

    soc/intel/apollolake: Add lpss dsdt entry
    
    Add southbridge and LPSS device DSDT table.
    
    Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1
    Signed-off-by: Zhao, Lijian <lijian.zhao at intel.com>
    (cherry picked from commit 866ef25ac6a1c3b96c5a6073d05fe7d672737752)
---
 src/soc/intel/apollolake/acpi/lpss.asl        | 111 ++++++++++++++++++++++++++
 src/soc/intel/apollolake/acpi/southbridge.asl |  15 ++++
 2 files changed, 126 insertions(+)

diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss.asl
new file mode 100644
index 0000000..d77eab0
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/lpss.asl
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+scope (\_SB.PCI0) {
+
+/* LPIO1 PWM */
+Device(PWM) {
+	Name (_ADR, 0x001A0000)
+	Name (_DDN, "Intel(R) PWM Controller")
+}
+
+/* LPIO1 HS-UART #1 */
+Device(URT1) {
+	Name (_ADR, 0x00180000)
+	Name (_DDN, "Intel(R) HS-UART Controller #1")
+}
+
+/* LPIO1 HS-UART #2 */
+Device(URT2) {
+	Name (_ADR, 0x00180001)
+	Name (_DDN, "Intel(R) HS-UART Controller #2")
+}
+
+/* LPIO1 HS-UART #3 */
+Device(URT3) {
+	Name (_ADR, 0x00180002)
+	Name (_DDN, "Intel(R) HS-UART Controller #3")
+}
+
+/* LPIO1 HS-UART #4 */
+Device(URT4) {
+	Name (_ADR, 0x00180003)
+	Name (_DDN, "Intel(R) HS-UART Controller #4")
+}
+
+/* LPIO1 SPI */
+Device(SPI1) {
+	Name (_ADR, 0x00190000)
+	Name (_DDN, "Intel(R) SPI Controller #1")
+}
+
+/* LPIO1 SPI #2 */
+Device(SPI2) {
+	Name (_ADR, 0x00190001)
+	Name (_DDN, "Intel(R) SPI Controller #2")
+}
+
+/* LPIO1 SPI #3 */
+Device(SPI3) {
+	Name (_ADR, 0x00190002)
+	Name (_DDN, "Intel(R) SPI Controller #3")
+}
+
+
+/* LPIO2 I2C #0 */
+Device(I2C0) {
+	Name (_ADR, 0x00160000)
+	Name (_DDN, "Intel(R) I2C Controller #0")
+}
+
+/* LPIO2 I2C #1 */
+Device(I2C1) {
+	Name (_ADR, 0x00160001)
+	Name (_DDN, "Intel(R) I2C Controller #1")
+}
+
+/* LPIO2 I2C #2 */
+Device(I2C2) {
+	Name (_ADR, 0x00160002)
+	Name (_DDN, "Intel(R) I2C Controller #2")
+}
+
+/* LPIO2 I2C #3 */
+Device(I2C3) {
+	Name (_ADR, 0x00160003)
+	Name (_DDN, "Intel(R) I2C Controller #3")
+}
+
+/* LPIO2 I2C #4 */
+Device(I2C4) {
+	Name (_ADR, 0x00170000)
+	Name (_DDN, "Intel(R) I2C Controller #4")
+}
+
+/* LPIO2 I2C #5 */
+Device(I2C5) {
+	Name (_ADR, 0x00170001)
+	Name (_DDN, "Intel(R) I2C Controller #5")
+}
+
+/* LPIO2 I2C #6 */
+Device(I2C6) {
+	Name (_ADR, 0x00170002)
+	Name (_DDN, "Intel(R) I2C Controller #6")
+}
+
+/* LPIO2 I2C #7 */
+Device(I2C7) {
+	Name (_ADR, 0x00170003)
+	Name (_DDN, "Intel(R) I2C Controller #7")
+}
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
new file mode 100644
index 0000000..7e9329f
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/* LPSS device */
+#include "lpss.asl"
+