[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI HPET table
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Fri Apr 1 07:14:58 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13374
-gerrit
commit bbfb0a7978646853034fde378b075c8aff68edf5
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date: Tue Dec 1 09:14:20 2015 -0800
soc/apollolake/acpi: Fill ACPI HPET table
HPET table is required to report integrated HPET timer to kernel.Without
HPET table insert,current kernel will panic in Timer driver.
Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0
Signed-off-by: Zhao, Lijian <lijian.zhao at intel.com>
---
src/soc/intel/apollolake/acpi.c | 7 ++++
src/soc/intel/apollolake/include/soc/acpi.h | 4 +++
src/soc/intel/apollolake/lpc.c | 54 +++++++++++++++++++++++++++++
3 files changed, 65 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index a12bb3c..0641621 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -108,3 +108,10 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt)
fadt->x_gpe1_blk.space_id = 1;
}
+
+unsigned long southbridge_write_acpi_tables(device_t device,
+ unsigned long current,
+ struct acpi_rsdp *rsdp)
+{
+ return acpi_write_hpet(device, current, rsdp);
+}
diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h
index f21b379..b57e083 100644
--- a/src/soc/intel/apollolake/include/soc/acpi.h
+++ b/src/soc/intel/apollolake/include/soc/acpi.h
@@ -15,6 +15,10 @@
#include <arch/acpi.h>
+/* Zero value won't be programmed again in FADT table. */
void soc_fill_common_fadt(acpi_fadt_t * fadt);
+unsigned long southbridge_write_acpi_tables(device_t device,
+ unsigned long current, struct acpi_rsdp *rsdp);
+
#endif /* _SOC_APOLLOLAKE_ACPI_H_ */
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
new file mode 100644
index 0000000..6d2e8ca
--- /dev/null
+++ b/src/soc/intel/apollolake/lpc.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/acpi.h>
+
+static void soc_lpc_add_io_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Add the default claimed legacy IO range for the LPC device. */
+ res = new_resource(dev, 0);
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void soc_lpc_read_resources(device_t dev)
+{
+ /* Get the PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add IO resources to LPC. */
+ soc_lpc_add_io_resources(dev);
+}
+
+static struct device_operations device_ops = {
+ .read_resources = &soc_lpc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .write_acpi_tables = southbridge_write_acpi_tables,
+};
+
+static const unsigned short pci_device_ids[] = {
+ 0x5AE8,
+ 0
+};
+
+static const struct pci_driver soc_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
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