[coreboot-gerrit] New patch to review for coreboot: skylake: select HAVE_INTEL_FIRMWARE

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11735

-gerrit

commit 17949b16d51d025641506bf08c213a799fdc3e18
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 30 13:41:01 2015 -0500

    skylake: select HAVE_INTEL_FIRMWARE
    
    Use the common ME and descriptor code.
    
    BUG=chrome-os-partner:43462
    BRANCH=None
    TEST=Built glados
    
    Change-Id: I7196f587b92fd26129b30e2cd73f4caf5f4ebef8
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/Kconfig      | 58 +-------------------------------------
 src/soc/intel/skylake/Makefile.inc | 36 -----------------------
 2 files changed, 1 insertion(+), 93 deletions(-)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 1ccde4a..ae50bd2 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -22,6 +22,7 @@ config CPU_SPECIFIC_OPTIONS
 	select GENERIC_GPIO_LIB
 	select HAS_PRECBMEM_TIMESTAMP_REGION
 	select HAVE_HARD_RESET
+	select HAVE_INTEL_FIRMWARE
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
 	select IOAPIC
@@ -85,38 +86,6 @@ config DCACHE_RAM_SIZE
 	  The size of the cache-as-ram region required during bootblock
 	  and/or romstage.
 
-config HAVE_IFD_BIN
-	bool "Use Intel Firmware Descriptor from existing binary"
-	default n
-
-config BUILD_WITH_FAKE_IFD
-	bool "Build with a fake IFD"
-	default y if !HAVE_IFD_BIN
-	help
-	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
-	  board, you can select this option and coreboot will build without it.
-	  Though, the resulting coreboot.rom will not contain all parts required
-	  to get coreboot running on your board. You can however write only the
-	  BIOS section to your board's flash ROM and keep the other sections
-	  untouched. Unfortunately the current version of flashrom doesn't
-	  support this yet. But there is a patch pending [1].
-
-	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
-		   was built with a fake IFD. It just won't work.
-
-	  [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
-
-config HAVE_ME_BIN
-	bool "Add Intel Management Engine firmware"
-	default y
-	help
-	  The Intel processor in the selected system requires a special firmware
-	  for an integrated controller called Management Engine (ME). The ME
-	  firmware might be provided in coreboot's 3rdparty/blobs repository. If
-	  not and if you don't have the firmware elsewhere, you can still
-	  build coreboot without it. In this case however, you'll have to make
-	  sure that you don't overwrite your ME firmware on your flash ROM.
-
 config HEAP_SIZE
 	hex
 	default 0x80000
@@ -125,31 +94,6 @@ config IED_REGION_SIZE
 	hex
 	default 0x400000
 
-config IFD_BIN_PATH
-	string "Path to intel firmware descriptor"
-	depends on !BUILD_WITH_FAKE_IFD
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-config IFD_BIOS_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_ME_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config IFD_PLATFORM_SECTION
-	depends on BUILD_WITH_FAKE_IFD
-	string
-	default ""
-
-config ME_BIN_PATH
-	string "Path to management engine firmware"
-	depends on HAVE_ME_BIN
-	default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
-
 config MMCONF_BASE_ADDRESS
 	hex "MMIO Base Address"
 	default 0xe0000000
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 38668da..d6bc839 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -67,40 +67,4 @@ CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 # Currently used for microcode path.
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE := pch_add_me
-
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
-IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
-		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
-		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
-else
-IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
-endif
-
-pch_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
-ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
-	printf "\n** WARNING **\n"
-	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
-	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
-	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
-	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
-	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
-endif
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(IFD_BIN_PATH) \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-ifeq ($(CONFIG_HAVE_ME_BIN),y)
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(CONFIG_ME_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += pch_add_me
-
 endif