[coreboot-gerrit] Patch merged into coreboot/master: Skylake:Set DISB inside romstage after mrc init

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 9ae6cd4280f0ff02711726393b74ca119fb1fc92
Author: Dhaval Sharma <dhaval.v.sharma at intel.com>
Date:   Thu Aug 27 17:13:19 2015 +0530

    Skylake:Set DISB inside romstage after mrc init
    
    Set DISB inside romstage right after successful mrc init such that
    any reset events afterwards can take fast boot path and in turn
    achieve better boot performance
    
    BRANCH=NONE
    BUG=chrome-os-partner:43637
    TEST=Built for kunimitsu and tested DISB is set correctly and fast
    boot path is taken.
    
    Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61
    Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00
    Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/295509
    Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma at intel.com>
    Original-Tested-by: dhaval v sharma <dhaval.v.sharma at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11550
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/11550 for details.

-gerrit