[coreboot-gerrit] New patch to review for coreboot: skylake: igd: clean up igd.c

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11564

-gerrit

commit f940efec62781e5aaa3168193298d5ec46da8f2e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:07:35 2015 -0700

    skylake: igd: clean up igd.c
    
    Remove unused constants, remove unused headers, and fix the
    use of acpi_slp_type variable.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I2d041f61605e0fc96483a1e825ab082668a0fa44
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: bc57147cb7fa3c38169fcdd62cc9e35d8058414a
    Original-Change-Id: If411ad50650e6705da7de50f5be8b1d414766a8c
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297741
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/igd.c | 24 +++++++++---------------
 1 file changed, 9 insertions(+), 15 deletions(-)

diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 25d89c3..5422217 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -26,21 +26,15 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <reg_script.h>
 #include <drivers/intel/gma/i915_reg.h>
 #include <soc/cpu.h>
 #include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
+#include <stdlib.h>
+#include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-#define GT_RETRY		1000
-#define GT_CDCLK_337		0
-#define GT_CDCLK_450		1
-#define GT_CDCLK_540		2
-#define GT_CDCLK_675		3
 u32 map_oprom_vendev(u32 vendev)
 {
 	return SA_IGD_OPROM_VENDEV;
@@ -80,16 +74,16 @@ static void igd_init(struct device *dev)
 		return;
 
 	/* Wait for any configured pre-graphics delay */
-	if (acpi_slp_type != SLEEP_STATE_S3) {
+	if (!acpi_is_wakeup_s3()) {
 #if IS_ENABLED(CONFIG_CHROMEOS)
-	if (developer_mode_enabled() || recovery_mode_enabled() ||
-	    vboot_wants_oprom())
-		mdelay(CONFIG_PRE_GRAPHICS_DELAY);
+		if (developer_mode_enabled() || recovery_mode_enabled() ||
+		    vboot_wants_oprom())
+			mdelay(CONFIG_PRE_GRAPHICS_DELAY);
 #else
-	mdelay(CONFIG_PRE_GRAPHICS_DELAY);
+		mdelay(CONFIG_PRE_GRAPHICS_DELAY);
 #endif
-
 	}
+
 	/* Initialize PCI device, load/execute BIOS Option ROM */
 	pci_dev_init(dev);
 
@@ -105,7 +99,7 @@ static void igd_init(struct device *dev)
 		gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
 			  DDI_INIT_DISPLAY_DETECTED);
 	}
-#endif /* CONFIG_CHROMEOS */
+#endif
 }
 
 static struct device_operations igd_ops = {