[coreboot-gerrit] New patch to review for coreboot: sklrvp: Clean up devicetree.cb

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11560

-gerrit

commit ea87bb296013551d8d1b7aea1b2a61f2f658334f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:03:09 2015 -0700

    sklrvp: Clean up devicetree.cb
    
    Remove devicetree.cb settings that do not apply to skylake so
    they can be removed from chip.h and clean up the pci device
    comments and add missing devices.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-sklrvp coreboot
    
    Change-Id: I232bd62853685bdcda771e3cbaba2d8ee7437b81
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a22e1fa56c68b06192acbeeb5c76862d84b8f509
    Original-Change-Id: I61f0581069d87ab974b0fffa6478b44a71bdd69b
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297337
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/sklrvp/devicetree.cb | 59 ++++++++++++--------------------
 1 file changed, 21 insertions(+), 38 deletions(-)

diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb
index cfa51a8..deb3ed7 100644
--- a/src/mainboard/intel/sklrvp/devicetree.cb
+++ b/src/mainboard/intel/sklrvp/devicetree.cb
@@ -45,24 +45,6 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "0x80"
 	register "pirqh_routing" = "0x80"
 
-	# EC range is 0x800-0x9ff
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x00fc0901"
-
-	# GPE configuration
-	register "gpe0_en_1" = "0x00000000"
-	# EC_SCI is GPIO36
-	register "gpe0_en_2" = "0x00000010"
-	register "gpe0_en_3" = "0x00000000"
-	register "gpe0_en_4" = "0x00000000"
-
-	# Force enable ASPM for PCIe Port 3
-	register "pcie_port_force_aspm" = "0x04"
-	register "pcie_port_coalesce" = "1"
-
-	# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
-	register "icc_clock_disable" = "0x013b0000"
-
 	# Enable S0ix
 	register "s0ix_enable" = "0"
 
@@ -113,25 +95,24 @@ chip soc/intel/skylake
 		device lapic 0 on end
 	end
 	device domain 0 on
-					# Refered from SKL EDS Vol 1 : Page No: 31-32
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 14.0 on  end # USB 3.0 xHCI Controller
-		device pci 14.1 off end # USB Device Controller (OTG)
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
-		device pci 15.0 on  end # I2C Controller #0
-		device pci 15.1 on  end # I2C Controller #1
-		device pci 15.2 on  end # I2C Controller #2
-		device pci 15.3 on  end # I2C Controller #3
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 on  end # I2C #2
+		device pci 15.3 on  end # I2C #3
 		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE Redirection (IDE-R)
-		device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection
-		device pci 16.4 off end # Management Engine Intel MEI #3
-		device pci 17.0 off end # SATA Controller
-		device pci 19.0 on  end # UART Controller #2
-		device pci 19.1 on  end # I2C Controller #5
-		device pci 19.2 on  end # I2C Controller #4
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT-Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 17.0 off end # SATA
+		device pci 19.0 on  end # UART #2
+		device pci 19.1 on  end # I2C #5
+		device pci 19.2 on  end # I2C #4
 		device pci 1c.0 off end # PCI Express Port 1
 		device pci 1c.1 off end # PCI Express Port 2
 		device pci 1c.2 off end # PCI Express Port 3
@@ -146,14 +127,16 @@ chip soc/intel/skylake
 		device pci 1d.3 off end # PCI Express Port 12
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 on  end # UART #1
-		device pci 1e.2 on  end # SPI #0
+		device pci 1e.2 on  end # GSPI #0
+		device pci 1e.3 on  end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
 		device pci 1e.6 on  end # SDCard
-		device pci 1f.0 on  end # LPC Interface (eSPI Enable Strap = 0) eSPI Interface (eSPI Enable Strap = 1)
-		device pci 1f.3 on  end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
-		device pci 1f.4 off end # SMBus Controller
-		device pci 1f.5 on  end # SPI
-		device pci 1f.6 off end # GbE Controller
+		device pci 1f.0 on  end # LPC Interface
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 off end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
 	end
 end