[coreboot-gerrit] New patch to review for coreboot: skylake: PCR: Add Port ID for SCS
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Sep 7 18:41:59 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11532
-gerrit
commit 36afa64e8c8573178c3c91d09a6250bf2c3184ef
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Thu Aug 27 16:35:06 2015 -0700
skylake: PCR: Add Port ID for SCS
Add the PCR Port ID for the storage controllers and
reformat to put the PCR PIDs in increasing order.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9
Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a
Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295905
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/skylake/include/soc/pcr.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h
index c8a4425..bf3161b 100644
--- a/src/soc/intel/skylake/include/soc/pcr.h
+++ b/src/soc/intel/skylake/include/soc/pcr.h
@@ -78,9 +78,10 @@
#define PID_GPIOCOM2 0xAD
#define PID_GPIOCOM1 0xAE
#define PID_GPIOCOM0 0xAF
-#define PID_LPC 0xC7
-#define PID_ITSS 0xC4
+#define PID_SCS 0xC0
#define PID_RTC 0xC3
+#define PID_ITSS 0xC4
+#define PID_LPC 0xC7
#define PID_SERIALIO 0xCB
#define PID_DMI 0xEF
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