[coreboot-gerrit] New patch to review for coreboot: mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Sat Oct 31 21:01:15 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12285
-gerrit
commit c77d236b605dcc6d2de9bb36032128da38ad0c2f
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Sat Oct 31 15:00:23 2015 -0500
mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support
TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed.
Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/mainboard/asus/kfsn4-dre_k8/Kconfig | 8 +++---
src/mainboard/asus/kfsn4-dre_k8/devicetree.cb | 5 +++-
src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c | 6 ++--
src/mainboard/asus/kfsn4-dre_k8/romstage.c | 39 +++++++++++++++-----------
4 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/src/mainboard/asus/kfsn4-dre_k8/Kconfig b/src/mainboard/asus/kfsn4-dre_k8/Kconfig
index bb05e95..4fa33ea 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/Kconfig
+++ b/src/mainboard/asus/kfsn4-dre_k8/Kconfig
@@ -35,15 +35,15 @@ config BOOTBLOCK_MAINBOARD_INIT
config DCACHE_RAM_BASE
hex
- default 0xcf000
+ default 0xc8000
config DCACHE_RAM_SIZE
hex
- default 0x01000
+ default 0x08000
config APIC_ID_OFFSET
hex
- default 0
+ default 0x10
config MAINBOARD_PART_NUMBER
string
@@ -63,7 +63,7 @@ config MAX_PHYSICAL_CPUS
config MEM_TRAIN_SEQ
int
- default 0
+ default 1
config HT_CHAIN_UNITID_BASE
hex
diff --git a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb
index 0eae379..a02b234 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb
+++ b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb
@@ -180,11 +180,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex
register "sata1_enable" = "1"
end
end
+ device pci 18.0 on end # Link 2 == LDT 2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
- device pci 19.0 on end
+ device pci 19.0 on end # Link 0 == LDT 0
+ device pci 19.0 on end # Link 1 == LDT 1
+ device pci 19.0 on end # Link 2 == LDT 2
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
index 8160457..d87bc3f 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
@@ -44,9 +44,9 @@ unsigned apicid_ck804;
/* Here you only need to set value in pci1234 for HT-IO that could be
installed or not You may need to preset pci1234 for HTIO board, please
-refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */
+refer to src/northbridge/amd/amdk8/get_pci1234.c for detail */
static u32 pci1234x[] = {
- 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+ 0x0000ff0, 0x0000ff0, 0x0000ff0,
};
@@ -54,7 +54,7 @@ static u32 pci1234x[] = {
in chain, assume every chain only have 4 ht device at most */
static unsigned hcdnx[] = {
- 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+ 0x20202020, 0x20202020, 0x20202020,
};
static unsigned get_bus_conf_done = 0;
diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
index 7098701..0c701df 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
@@ -66,6 +66,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include <spd.h>
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
+#include "northbridge/amd/amdk8/early_ht.c"
#define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/
@@ -199,7 +200,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
- u32 bsp_apicid = 0, val, wants_reset, needs_reset;
+ uint32_t bsp_apicid = 0;
+ uint32_t dword;
+ uint8_t needs_reset = 0;
#if IS_ENABLED(CONFIG_SET_FIDVID)
struct cpuid_result cpuid1;
#endif
@@ -207,8 +210,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
- if (!cpu_init_detectedx && boot_cpu())
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ enumerate_ht_chain();
sio_setup();
+ }
post_code(0x30);
@@ -226,8 +233,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ dword = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", dword);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
@@ -240,19 +247,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
post_code(0x35);
- /* Setup any mainboard PCI settings etc. */
- setup_mb_resource_map();
- post_code(0x36);
-
/* Wait for all base cores to start */
wait_all_core0_started();
+ post_code(0x36);
+
+ /* Setup any mainboard PCI settings etc. */
+ setup_mb_resource_map();
+ post_code(0x37);
if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
- post_code(0x37);
+ post_code(0x38);
wait_all_other_cores_started(bsp_apicid);
+ post_code(0x39);
}
ht_setup_chains_x(sysinfo);
@@ -280,18 +289,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif
+ init_timer(); /* Need to use TMICT to synchronize FID/VID. */
+
printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n");
ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID);
- post_code(0x38);
-
- printk(BIOS_DEBUG, "ck804_early_setup_x()\n");
- wants_reset = ck804_early_setup_x();
+ post_code(0x3a);
printk(BIOS_DEBUG, "optimize_link_coherent_ht()\n");
needs_reset = optimize_link_coherent_ht();
printk(BIOS_DEBUG, "optimize_link_incoherent_ht()\n");
needs_reset |= optimize_link_incoherent_ht(sysinfo);
+ printk(BIOS_DEBUG, "ck804_early_setup_x()\n");
+ needs_reset |= ck804_early_setup_x();
/* FIDVID change will issue one LDTSTOP and the HT change will be effective too */
if (needs_reset) {
@@ -299,9 +309,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
soft_reset();
}
- if (wants_reset)
- printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n");
-
post_code(0x3b);
allow_all_aps_stop(bsp_apicid);
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