[coreboot-gerrit] Patch set updated for coreboot: cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstage

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12250

-gerrit

commit 6cb9e9f2383210b0deef541982ca17407b9f3c76
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Thu Oct 29 01:33:25 2015 -0500

    cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstage
    
    This mirrors a similar commit made to Family 10h support
    in changeset 11966 file model_10xxx_init.c
    
    TEST: Booted ASS KFSN4-DRE with 1x Opteron 8222
    
    Change-Id: I760ef27be00aed11c0ac21b9bd741189f4b05834
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/cpu/amd/model_fxx/model_fxx_init.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index db936f8..93fa07f 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -460,6 +460,18 @@ static void model_fxx_init(device_t dev)
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
+
+	/* Initialize all variable MTRRs except the first pair */
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000000;
+
+	disable_cache();
+
+	for (i = 0x2; i < 0x10; i++) {
+		wrmsr(0x00000200 | i, msr);
+	}
+
+	enable_cache();
 	amd_setup_mtrrs();
 	x86_mtrr_check();