[coreboot-gerrit] New patch to review for coreboot: skylake: Set Pkg Power clamping bit in Power Limit MSR

Patrick Georgi (pgeorgi@google.com) gerrit at coreboot.org
Thu Oct 29 21:08:21 CET 2015


Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12257

-gerrit

commit a3589c35132eed06f5349b51c48cf1a15b813354
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Thu Oct 15 21:38:21 2015 +0530

    skylake: Set Pkg Power clamping bit in Power Limit MSR
    
    Setting the Package Power clamping bits in Power Limit MSR
    (MSR_PKG_POWER_LIMIT 0x610) Allows going below the OS requested
    P or T state for the time window specified for PL1 or PL2.
    
    BRANCH=none
    BUG=chrome-os-partner:47041
    TEST=Built and boot on kunimitsu, load the system with Aquarium WebGL,
    	change the power limit value from default (TDP or 15W) to any lower value
    	note that the Pkg power comes down and also the CPU frequency is lowered.
    
    Change-Id: I9c0dd90a6660214ae142418aae8b8c5f6a739896
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: b0b527991c2d26da5772700a22ff101eaf9993ef
    Original-Change-Id: Ia59fcfe2a14cd7f8b1e1b8e967073e67eb452f42
    Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/309556
    Original-Tested-by: Charulatha Varadarajan <charuprasanna at gmail.com>
    Original-Tested-by: Charulatha Varadarajan <charulatha.varadarajan at intel.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index ba1a96c..9e9e254 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -156,6 +156,10 @@ void set_power_limits(u8 power_limit_1_time)
 	/* Set long term power limit to TDP */
 	limit.lo = 0;
 	limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+
+	/* Set PL1 Pkg Power clamp bit */
+	limit.lo |= PKG_POWER_LIMIT_CLAMP;
+
 	limit.lo |= PKG_POWER_LIMIT_EN;
 	limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
 		PKG_POWER_LIMIT_TIME_SHIFT;
@@ -163,6 +167,7 @@ void set_power_limits(u8 power_limit_1_time)
 	/* Set short term power limit to 1.25 * TDP */
 	limit.hi = 0;
 	limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+	limit.hi |= PKG_POWER_LIMIT_CLAMP;
 	limit.hi |= PKG_POWER_LIMIT_EN;
 
 	/* Power limit 2 time is only programmable on server SKU */



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