[coreboot-gerrit] New patch to review for coreboot: Drop southbridge intel/esb6300
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Thu Oct 29 02:18:24 CET 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12238
-gerrit
commit e5825da36689078750f07a582fc8aa78b27a6f87
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Wed Oct 28 18:02:35 2015 -0700
Drop southbridge intel/esb6300
All mainboards using this southbridge have been removed from
the tree already.
Change-Id: I4398ef1e270bd0f36c5dd1c6ec3bfec6c2c091e6
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
src/southbridge/intel/esb6300/Kconfig | 4 -
src/southbridge/intel/esb6300/Makefile.inc | 16 --
src/southbridge/intel/esb6300/ac97.c | 37 ---
src/southbridge/intel/esb6300/bridge1c.c | 46 ----
src/southbridge/intel/esb6300/chip.h | 28 ---
src/southbridge/intel/esb6300/early_smbus.c | 97 --------
src/southbridge/intel/esb6300/ehci.c | 50 ----
src/southbridge/intel/esb6300/esb6300.c | 48 ----
src/southbridge/intel/esb6300/esb6300.h | 7 -
src/southbridge/intel/esb6300/ide.c | 55 ----
src/southbridge/intel/esb6300/lpc.c | 374 ----------------------------
src/southbridge/intel/esb6300/pci.c | 36 ---
src/southbridge/intel/esb6300/pic.c | 67 -----
src/southbridge/intel/esb6300/reset.c | 27 --
src/southbridge/intel/esb6300/sata.c | 74 ------
src/southbridge/intel/esb6300/smbus.c | 48 ----
src/southbridge/intel/esb6300/smbus.h | 100 --------
src/southbridge/intel/esb6300/uhci.c | 56 -----
18 files changed, 1170 deletions(-)
diff --git a/src/southbridge/intel/esb6300/Kconfig b/src/southbridge/intel/esb6300/Kconfig
deleted file mode 100644
index 01f719e..0000000
--- a/src/southbridge/intel/esb6300/Kconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-config SOUTHBRIDGE_INTEL_ESB6300
- bool
- select IOAPIC
- select HAVE_HARD_RESET
diff --git a/src/southbridge/intel/esb6300/Makefile.inc b/src/southbridge/intel/esb6300/Makefile.inc
deleted file mode 100644
index fba8c23..0000000
--- a/src/southbridge/intel/esb6300/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_ESB6300),y)
-
-ramstage-y += esb6300.c
-ramstage-y += reset.c
-ramstage-y += uhci.c
-ramstage-y += lpc.c
-ramstage-y += ide.c
-ramstage-y += sata.c
-ramstage-y += ehci.c
-ramstage-y += smbus.c
-ramstage-y += pci.c
-ramstage-y += pic.c
-ramstage-y += bridge1c.c
-ramstage-y += ac97.c
-
-endif
diff --git a/src/southbridge/intel/esb6300/ac97.c b/src/southbridge/intel/esb6300/ac97.c
deleted file mode 100644
index 7b7795f..0000000
--- a/src/southbridge/intel/esb6300/ac97.c
+++ /dev/null
@@ -1,37 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "esb6300.h"
-
-static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
- /* Write the subsystem vendor and device id */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = ac97_set_subsystem,
-};
-static struct device_operations ac97_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = 0,
- .enable = esb6300_enable,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver ac97_audio_driver __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_AC97_AUDIO,
-};
-static const struct pci_driver ac97_modem_driver __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_AC97_MODEM,
-};
diff --git a/src/southbridge/intel/esb6300/bridge1c.c b/src/southbridge/intel/esb6300/bridge1c.c
deleted file mode 100644
index 8af1fd6..0000000
--- a/src/southbridge/intel/esb6300/bridge1c.c
+++ /dev/null
@@ -1,46 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "esb6300.h"
-
-static void bridge1c_init(struct device *dev)
-{
- /* configuration */
- pci_write_config8(dev, 0x1b, 0x30);
-// pci_write_config8(dev, 0x3e, 0x07);
- pci_write_config8(dev, 0x3e, 0x04); /* parity ignore */
- pci_write_config8(dev, 0x6c, 0x0c); /* undocumented */
- pci_write_config8(dev, 0xe0, 0x20);
-
- /* SRB enable */
- pci_write_config16(dev, 0xe4, 0x0232);
-
- /* Burst size */
- pci_write_config8(dev, 0xf0, 0x02);
-
- /* prefetch threshold size */
- pci_write_config16(dev, 0xf8, 0x2121);
-
- /* primary latency */
- pci_write_config8(dev, 0x0d, 0x28);
-
- /* multi transaction timer */
- pci_write_config8(dev, 0x42, 0x08);
-}
-
-static struct device_operations pci_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = bridge1c_init,
- .scan_bus = pci_scan_bridge,
- .ops_pci = 0,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_PCI_X,
-};
diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h
deleted file mode 100644
index 384a991..0000000
--- a/src/southbridge/intel/esb6300/chip.h
+++ /dev/null
@@ -1,28 +0,0 @@
-struct southbridge_intel_esb6300_config
-{
-#define ESB6300_GPIO_USE_MASK 0x03
-#define ESB6300_GPIO_USE_DEFAULT 0x00
-#define ESB6300_GPIO_USE_AS_NATIVE 0x01
-#define ESB6300_GPIO_USE_AS_GPIO 0x02
-
-#define ESB6300_GPIO_SEL_MASK 0x0c
-#define ESB6300_GPIO_SEL_DEFAULT 0x00
-#define ESB6300_GPIO_SEL_OUTPUT 0x04
-#define ESB6300_GPIO_SEL_INPUT 0x08
-
-#define ESB6300_GPIO_LVL_MASK 0x30
-#define ESB6300_GPIO_LVL_DEFAULT 0x00
-#define ESB6300_GPIO_LVL_LOW 0x10
-#define ESB6300_GPIO_LVL_HIGH 0x20
-#define ESB6300_GPIO_LVL_BLINK 0x30
-
-#define ESB6300_GPIO_INV_MASK 0xc0
-#define ESB6300_GPIO_INV_DEFAULT 0x00
-#define ESB6300_GPIO_INV_OFF 0x40
-#define ESB6300_GPIO_INV_ON 0x80
-
- /* GPIO use select */
- unsigned char gpio[64];
- unsigned int pirq_a_d;
- unsigned int pirq_e_h;
-};
diff --git a/src/southbridge/intel/esb6300/early_smbus.c b/src/southbridge/intel/esb6300/early_smbus.c
deleted file mode 100644
index 9ad4f65..0000000
--- a/src/southbridge/intel/esb6300/early_smbus.c
+++ /dev/null
@@ -1,97 +0,0 @@
-#include "smbus.h"
-
-#define SMBUS_IO_BASE 0x0f00
-
-static void enable_smbus(void)
-{
- device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
-
- printk(BIOS_SPEW, "SMBus controller enabled\n");
- pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
- pci_write_config8(dev, 0x40, 1);
- pci_write_config8(dev, 0x4, 1);
- /* SMBALERT_DIS */
- pci_write_config8(dev, 0x11, 4);
-
- /* Disable interrupt generation */
- outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-}
-
-static int smbus_read_byte(unsigned device, unsigned address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-#ifdef DEADCODE
-static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
-{
- if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
- return;
- }
- return;
-}
-
-static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
- unsigned data1, unsigned data2)
-{
- unsigned char byte;
- unsigned char stat;
- int i;
-
- /* chear the PM timeout flags, SECOND_TO_STS */
- outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
-
- if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
- return -2;
- }
-
- /* setup transaction */
- /* Obtain ownership */
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- for(stat=0;(stat&0x40)==0;) {
- stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
- }
- /* clear the done bit */
- outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
- /* disable interrupts */
- outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
-
- /* set the command address */
- outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-
- /* set the block length */
- outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
-
- /* try sending out the first byte of data here */
- byte=(data1>>(0))&0x0ff;
- outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
- /* issue a block write command */
- outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
- SMBUS_IO_BASE + SMBHSTCTL);
-
- for(i=0;i<length;i++) {
-
- /* poll for transaction completion */
- if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
- return -3;
- }
-
- /* load the next byte */
- if(i>3)
- byte=(data2>>(i%4))&0x0ff;
- else
- byte=(data1>>(i))&0x0ff;
- outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
-
- /* clear the done bit */
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
- SMBUS_IO_BASE + SMBHSTSTAT);
- }
-
- printk(BIOS_DEBUG, "SMBUS Block complete\n");
- return 0;
-}
-#endif
diff --git a/src/southbridge/intel/esb6300/ehci.c b/src/southbridge/intel/esb6300/ehci.c
deleted file mode 100644
index c103c4b..0000000
--- a/src/southbridge/intel/esb6300/ehci.c
+++ /dev/null
@@ -1,50 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "esb6300.h"
-
-static void ehci_init(struct device *dev)
-{
- uint32_t cmd;
-
- printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
- cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
- cmd | PCI_COMMAND_MASTER);
-
- printk(BIOS_DEBUG, "done.\n");
-}
-
-static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
- uint8_t access_cntl;
- access_cntl = pci_read_config8(dev, 0x80);
- /* Enable writes to protected registers */
- pci_write_config8(dev, 0x80, access_cntl | 1);
- /* Write the subsystem vendor and device id */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
- /* Restore protection */
- pci_write_config8(dev, 0x80, access_cntl);
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = &ehci_set_subsystem,
-};
-static struct device_operations ehci_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ehci_init,
- .scan_bus = 0,
- .enable = esb6300_enable,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver ehci_driver __pci_driver = {
- .ops = &ehci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_EHCI,
-};
diff --git a/src/southbridge/intel/esb6300/esb6300.c b/src/southbridge/intel/esb6300/esb6300.c
deleted file mode 100644
index 5d8f5e4..0000000
--- a/src/southbridge/intel/esb6300/esb6300.c
+++ /dev/null
@@ -1,48 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "esb6300.h"
-
-void esb6300_enable(device_t dev)
-{
- device_t lpc_dev;
- unsigned index = 0;
- uint16_t reg_old, reg;
-
- /* See if we are on the behind the 6300 pci bridge */
- lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
- if((dev->path.pci.devfn &0xf8)== 0xf8) {
- index = dev->path.pci.devfn & 7;
- }
- else if((dev->path.pci.devfn &0xf8)== 0xe8) {
- index = (dev->path.pci.devfn & 7) +8;
- }
- if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
- return;
- }
- if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
- (lpc_dev->device != PCI_DEVICE_ID_INTEL_6300ESB_LPC)) {
- uint32_t id;
- id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
- if (id != (PCI_VENDOR_ID_INTEL |
- (PCI_DEVICE_ID_INTEL_6300ESB_LPC << 16))) {
- return;
- }
- }
-
- reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
- reg &= ~(1 << index);
- if (!dev->enabled) {
- reg |= (1 << index);
- }
- if (reg != reg_old) {
- pci_write_config16(lpc_dev, 0xf2, reg);
- }
-
-}
-
-struct chip_operations southbridge_intel_esb6300_ops = {
- CHIP_NAME("Intel 6300ESB Southbridge")
- .enable_dev = esb6300_enable,
-};
diff --git a/src/southbridge/intel/esb6300/esb6300.h b/src/southbridge/intel/esb6300/esb6300.h
deleted file mode 100644
index 2c91fcb..0000000
--- a/src/southbridge/intel/esb6300/esb6300.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef ESB6300_H
-#define ESB6300_H
-#include "chip.h"
-
-void esb6300_enable(device_t dev);
-
-#endif /* ESB6300 */
diff --git a/src/southbridge/intel/esb6300/ide.c b/src/southbridge/intel/esb6300/ide.c
deleted file mode 100644
index 39e58da..0000000
--- a/src/southbridge/intel/esb6300/ide.c
+++ /dev/null
@@ -1,55 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "esb6300.h"
-
-static void ide_init(struct device *dev)
-{
-
- /* Enable ide devices so the linux ide driver will work */
-
- /* Enable IDE devices */
- pci_write_config16(dev, 0x40, 0x0a307);
- pci_write_config16(dev, 0x42, 0x0a307);
- pci_write_config8(dev, 0x48, 0x05);
- pci_write_config16(dev, 0x4a, 0x0101);
- pci_write_config16(dev, 0x54, 0x5055);
-
-#if 0
- uint16_t word;
- word = pci_read_config16(dev, 0x40);
- word |= (1 << 15);
- pci_write_config16(dev, 0x40, word);
- word = pci_read_config16(dev, 0x42);
- word |= (1 << 15);
- pci_write_config16(dev, 0x42, word);
-#endif
- printk(BIOS_DEBUG, "IDE Enabled\n");
-}
-
-static void esb6300_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
- /* This value is also visible in uchi[0-2] and smbus functions */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = esb6300_ide_set_subsystem,
-};
-static struct device_operations ide_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ide_init,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver ide_driver __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_IDE,
-};
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c
deleted file mode 100644
index e1718bb..0000000
--- a/src/southbridge/intel/esb6300/lpc.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
- * (C) 2004 Linux Networx
- */
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/isa-dma.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include "esb6300.h"
-
-#define ACPI_BAR 0x40
-#define GPIO_BAR 0x58
-
-#define NMI_OFF 0
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
-
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-#define SERIRQ_CNTL 0x64
-static void esb6300_enable_serial_irqs(device_t dev)
-{
- /* set packet length and toggle silent mode bit */
- pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
- pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
-}
-
-#define PCI_DMA_CFG 0x90
-static void esb6300_pci_dma_cfg(device_t dev)
-{
- /* Set PCI DMA CFG to lpc I/F DMA */
- pci_write_config16(dev, PCI_DMA_CFG, 0xfcff);
-}
-
-#define LPC_EN 0xe6
-static void esb6300_enable_lpc(device_t dev)
-{
- /* lpc i/f enable */
- pci_write_config8(dev, LPC_EN, 0x0d);
-}
-
-typedef struct southbridge_intel_esb6300_config config_t;
-
-static void set_esb6300_gpio_use_sel(
- device_t dev, struct resource *res, config_t *config)
-{
- uint32_t gpio_use_sel, gpio_use_sel2;
-
-// gpio_use_sel = 0x1B003100;
-// gpio_use_sel2 = 0x03000000;
- gpio_use_sel = 0x1BBC31C0;
- gpio_use_sel2 = 0x03000FE1;
-#if 0
- int i;
- for(i = 0; i < 64; i++) {
- int val;
- switch(config->gpio[i] & ESB6300_GPIO_USE_MASK) {
- case ESB6300_GPIO_USE_AS_NATIVE: val = 0; break;
- case ESB6300_GPIO_USE_AS_GPIO: val = 1; break;
- default:
- continue;
- }
- /* The caller is responsible for not playing with unimplemented bits */
- if (i < 32) {
- gpio_use_sel &= ~( 1 << i);
- gpio_use_sel |= (val << i);
- } else {
- gpio_use_sel2 &= ~( 1 << (i - 32));
- gpio_use_sel2 |= (val << (i - 32));
- }
- }
-#endif
- outl(gpio_use_sel, res->base + 0x00);
- outl(gpio_use_sel2, res->base + 0x30);
-}
-
-static void set_esb6300_gpio_direction(
- device_t dev, struct resource *res, config_t *config)
-{
- uint32_t gpio_io_sel, gpio_io_sel2;
-
-// gpio_io_sel = 0x0000ffff;
-// gpio_io_sel2 = 0x00000000;
- gpio_io_sel = 0x1900ffff;
- gpio_io_sel2 = 0x00000fe1;
-#if 0
- int i;
- for(i = 0; i < 64; i++) {
- int val;
- switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) {
- case ESB6300_GPIO_SEL_OUTPUT: val = 0; break;
- case ESB6300_GPIO_SEL_INPUT: val = 1; break;
- default:
- continue;
- }
- /* The caller is responsible for not playing with unimplemented bits */
- if (i < 32) {
- gpio_io_sel &= ~( 1 << i);
- gpio_io_sel |= (val << i);
- } else {
- gpio_io_sel2 &= ~( 1 << (i - 32));
- gpio_io_sel2 |= (val << (i - 32));
- }
- }
-#endif
- outl(gpio_io_sel, res->base + 0x04);
- outl(gpio_io_sel2, res->base + 0x34);
-}
-
-static void set_esb6300_gpio_level(
- device_t dev, struct resource *res, config_t *config)
-{
- uint32_t gpio_lvl, gpio_lvl2;
- uint32_t gpio_blink;
-
-// gpio_lvl = 0x1b3f0000;
-// gpio_blink = 0x00040000;
-// gpio_lvl2 = 0x00000fff;
- gpio_lvl = 0x19370000;
- gpio_blink = 0x00000000;
- gpio_lvl2 = 0x00000fff;
-#if 0
- int i;
- for(i = 0; i < 64; i++) {
- int val, blink;
- switch(config->gpio[i] & ESB6300_GPIO_LVL_MASK) {
- case ESB6300_GPIO_LVL_LOW: val = 0; blink = 0; break;
- case ESB6300_GPIO_LVL_HIGH: val = 1; blink = 0; break;
- case ESB6300_GPIO_LVL_BLINK: val = 1; blink = 1; break;
- default:
- continue;
- }
- /* The caller is responsible for not playing with unimplemented bits */
- if (i < 32) {
- gpio_lvl &= ~( 1 << i);
- gpio_blink &= ~( 1 << i);
- gpio_lvl |= ( val << i);
- gpio_blink |= (blink << i);
- } else {
- gpio_lvl2 &= ~( 1 << (i - 32));
- gpio_lvl2 |= (val << (i - 32));
- }
- }
-#endif
- outl(gpio_lvl, res->base + 0x0c);
- outl(gpio_blink, res->base + 0x18);
- outl(gpio_lvl2, res->base + 0x38);
-}
-
-static void set_esb6300_gpio_inv(
- device_t dev, struct resource *res, config_t *config)
-{
- uint32_t gpio_inv;
-
- gpio_inv = 0x00003100;
-#if 0
- int i;
- for(i = 0; i < 32; i++) {
- int val;
- switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) {
- case ESB6300_GPIO_INV_OFF: val = 0; break;
- case ESB6300_GPIO_INV_ON: val = 1; break;
- default:
- continue;
- }
- gpio_inv &= ~( 1 << i);
- gpio_inv |= (val << i);
- }
-#endif
- outl(gpio_inv, res->base + 0x2c);
-}
-
-static void esb6300_pirq_init(device_t dev)
-{
- config_t *config;
-
- /* Get the chip configuration */
- config = dev->chip_info;
-
- if(config->pirq_a_d) {
- pci_write_config32(dev, 0x60, config->pirq_a_d);
- }
- if(config->pirq_e_h) {
- pci_write_config32(dev, 0x68, config->pirq_e_h);
- }
-}
-
-
-static void esb6300_gpio_init(device_t dev)
-{
- struct resource *res;
- config_t *config;
-
- /* Skip if I don't have any configuration */
- if (!dev->chip_info) {
- return;
- }
- /* The programmer is responsible for ensuring
- * a valid gpio configuration.
- */
-
- /* Get the chip configuration */
- config = dev->chip_info;
- /* Find the GPIO bar */
- res = find_resource(dev, GPIO_BAR);
- if (!res) {
- return;
- }
-
- /* Set the use selects */
- set_esb6300_gpio_use_sel(dev, res, config);
-
- /* Set the IO direction */
- set_esb6300_gpio_direction(dev, res, config);
-
- /* Setup the input inverters */
- set_esb6300_gpio_inv(dev, res, config);
-
- /* Set the value on the GPIO output pins */
- set_esb6300_gpio_level(dev, res, config);
-
-}
-
-
-static void lpc_init(struct device *dev)
-{
- uint8_t byte;
- uint32_t value;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
-
- /* sata settings */
- pci_write_config32(dev, 0x58, 0x00001181);
-
- /* IO APIC initialization */
- value = pci_read_config32(dev, 0xd0);
- value |= (1 << 8)|(1<<7);
- value |= (6 << 0)|(1<<13)|(1<<11);
- pci_write_config32(dev, 0xd0, value);
- setup_ioapic(VIO_APIC_VADDR, 0); // don't rename IO APIC ID
-
- /* disable reset timer */
- pci_write_config8(dev, 0xd4, 0x02);
-
- /* cmos ram 2nd 128 */
- pci_write_config8(dev, 0xd8, 0x04);
-
- /* comm 2 */
- pci_write_config8(dev, 0xe0, 0x10);
-
- /* fwh sellect */
- pci_write_config32(dev, 0xe8, 0x00112233);
-
- /* fwh decode */
- pci_write_config8(dev, 0xf0, 0x0f);
-
- /* av disable, sata controller */
- pci_write_config8(dev, 0xf2, 0xc0);
-
- /* undocumented */
- pci_write_config8(dev, 0xa0, 0x20);
- pci_write_config8(dev, 0xad, 0x03);
- pci_write_config8(dev, 0xbb, 0x09);
-
- /* apic1 rout */
- pci_write_config8(dev, 0xf4, 0x40);
-
- /* undocumented */
- pci_write_config8(dev, 0xa0, 0x20);
- pci_write_config8(dev, 0xad, 0x03);
- pci_write_config8(dev, 0xbb, 0x09);
-
- esb6300_enable_serial_irqs(dev);
-
- esb6300_pci_dma_cfg(dev);
-
- esb6300_enable_lpc(dev);
-
- get_option(&pwr_on, "power_on_after_fail");
- byte = pci_read_config8(dev, 0xa4);
- byte &= 0xfe;
- if (!pwr_on) {
- byte |= 1;
- }
- pci_write_config8(dev, 0xa4, byte);
- printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
-
- /* Set up the PIRQ */
- esb6300_pirq_init(dev);
-
- /* Set the state of the gpio lines */
- esb6300_gpio_init(dev);
-
- /* Initialize the real time clock */
- cmos_init(0);
-
- /* Initialize isa dma */
- isa_dma_init();
-}
-
-static void esb6300_lpc_read_resources(device_t dev)
-{
- struct resource *res;
-
- /* Get the normal pci resources of this device */
- pci_dev_read_resources(dev);
-
- /* Add the ACPI BAR */
- res = pci_get_resource(dev, ACPI_BAR);
-
- /* Add the GPIO BAR */
- res = pci_get_resource(dev, GPIO_BAR);
-
- /* Add an extra subtractive resource for both memory and I/O. */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->base = 0;
- res->size = 0x1000;
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->base = 0xff800000;
- res->size = 0x00800000; /* 8 MB for flash */
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = IO_APIC_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void esb6300_lpc_enable_resources(device_t dev)
-{
- uint8_t acpi_cntl, gpio_cntl;
-
- /* Enable the normal pci resources */
- pci_dev_enable_resources(dev);
-
- /* Enable the ACPI bar */
- acpi_cntl = pci_read_config8(dev, 0x44);
- acpi_cntl |= (1 << 4);
- pci_write_config8(dev, 0x44, acpi_cntl);
-
- /* Enable the GPIO bar */
- gpio_cntl = pci_read_config8(dev, 0x5c);
- gpio_cntl |= (1 << 4);
- pci_write_config8(dev, 0x5c, gpio_cntl);
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = 0,
-};
-
-static struct device_operations lpc_ops = {
- .read_resources = esb6300_lpc_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = esb6300_lpc_enable_resources,
- .init = lpc_init,
- .scan_bus = scan_lpc_bus,
- .enable = esb6300_enable,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_LPC,
-};
diff --git a/src/southbridge/intel/esb6300/pci.c b/src/southbridge/intel/esb6300/pci.c
deleted file mode 100644
index 991cd7b..0000000
--- a/src/southbridge/intel/esb6300/pci.c
+++ /dev/null
@@ -1,36 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "esb6300.h"
-
-static void pci_init(struct device *dev)
-{
-
- uint16_t word;
-
- /* Clear system errors */
- word = pci_read_config16(dev, 0x06);
- word |= 0xf900; /* Clear possible errors */
- pci_write_config16(dev, 0x06, word);
-
- word = pci_read_config16(dev, 0x1e);
- word |= 0xf800; /* Clear possible errors */
- pci_write_config16(dev, 0x1e, word);
-}
-
-static struct device_operations pci_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pci_init,
- .scan_bus = pci_scan_bridge,
- .ops_pci = 0,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_PCI,
-};
diff --git a/src/southbridge/intel/esb6300/pic.c b/src/southbridge/intel/esb6300/pic.c
deleted file mode 100644
index c453ca3..0000000
--- a/src/southbridge/intel/esb6300/pic.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * (C) 2004 Linux Networx
- */
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/ioapic.h>
-#include "esb6300.h"
-
-static void pic_init(struct device *dev)
-{
-
- uint16_t word;
-
- /* Clear system errors */
- word = pci_read_config16(dev, 0x06);
- word |= 0xf900; /* Clear possible errors */
- pci_write_config16(dev, 0x06, word);
-
- /* enable interrupt lines */
- pci_write_config8(dev, 0x3c, 0xff);
-
- /* Setup the ioapic */
- clear_ioapic((void *)(IO_APIC_ADDR + 0x10000));
-}
-
-static void pic_read_resources(device_t dev)
-{
- struct resource *res;
-
- /* Get the normal pci resources of this device */
- pci_dev_read_resources(dev);
-
- /* Report the pic1 mbar resource */
- res = new_resource(dev, 0x44);
- res->base = IO_APIC_ADDR + 0x10000;
- res->size = 256;
- res->limit = res->base + res->size -1;
- res->align = 8;
- res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_ASSIGNED;
- dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
-}
-
-static struct pci_operations lops_pci = {
- /* Can we set the pci subsystem and device id? */
- .set_subsystem = 0,
-};
-
-static struct device_operations pci_ops = {
- .read_resources = pic_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = pic_init,
- .scan_bus = 0,
- .enable = esb6300_enable,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_APIC1,
-};
diff --git a/src/southbridge/intel/esb6300/reset.c b/src/southbridge/intel/esb6300/reset.c
deleted file mode 100644
index 77787a5..0000000
--- a/src/southbridge/intel/esb6300/reset.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ronald G. Minnich
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void hard_reset(void)
-{
- /* Try rebooting through port 0xcf9 */
- outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
diff --git a/src/southbridge/intel/esb6300/sata.c b/src/southbridge/intel/esb6300/sata.c
deleted file mode 100644
index b08f0ed..0000000
--- a/src/southbridge/intel/esb6300/sata.c
+++ /dev/null
@@ -1,74 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "esb6300.h"
-
-static void sata_init(struct device *dev)
-{
- /* Enable sata devices so the linux sata driver will work */
-
- /* Enable SATA devices */
-
- printk(BIOS_DEBUG, "SATA init\n");
- /* SATA configuration */
- pci_write_config8(dev, 0x04, 0x07);
- pci_write_config8(dev, 0x09, 0x8f);
-
- /* Set timmings */
- pci_write_config16(dev, 0x40, 0x0a307);
- pci_write_config16(dev, 0x42, 0x0a307);
-
- /* Sync DMA */
- pci_write_config16(dev, 0x48, 0x000f);
- pci_write_config16(dev, 0x4a, 0x1111);
-
- /* 66 mhz */
- pci_write_config16(dev, 0x54, 0xf00f);
-
- /* Combine ide - sata configuration */
- pci_write_config8(dev, 0x90, 0x0);
-
- /* port 0 & 1 enable */
- pci_write_config8(dev, 0x92, 0x33);
-
- /* initialize SATA */
- pci_write_config16(dev, 0xa0, 0x0018);
- pci_write_config32(dev, 0xa4, 0x00000264);
- pci_write_config16(dev, 0xa0, 0x0040);
- pci_write_config32(dev, 0xa4, 0x00220043);
-
- printk(BIOS_DEBUG, "SATA Enabled\n");
-}
-
-static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
- /* This value is also visible in usb1, usb2 and smbus functions */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = esb6300_sata_set_subsystem,
-};
-static struct device_operations sata_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = sata_init,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver sata_driver __pci_driver = {
- .ops = &sata_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA,
-};
-
-static const struct pci_driver sata_driver_nr __pci_driver = {
- .ops = &sata_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA_RAID,
-};
diff --git a/src/southbridge/intel/esb6300/smbus.c b/src/southbridge/intel/esb6300/smbus.c
deleted file mode 100644
index 2c026b8..0000000
--- a/src/southbridge/intel/esb6300/smbus.c
+++ /dev/null
@@ -1,48 +0,0 @@
-#include <device/device.h>
-#include <device/path.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/smbus.h>
-#include <arch/io.h>
-#include "esb6300.h"
-#include "smbus.h"
-
-static int lsmbus_read_byte(device_t dev, u8 address)
-{
- u16 device;
- struct resource *res;
- struct bus *pbus;
-
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x20);
-
- return do_smbus_read_byte(res->base, device, address);
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
- .read_byte = lsmbus_read_byte,
-};
-
-static struct pci_operations lops_pci = {
- /* The subsystem id follows the ide controller */
- .set_subsystem = 0,
-};
-
-static struct device_operations smbus_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = scan_smbus,
- .enable = esb6300_enable,
- .ops_pci = &lops_pci,
- .ops_smbus_bus = &lops_smbus_bus,
-};
-
-static const struct pci_driver smbus_driver __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_SMB,
-};
diff --git a/src/southbridge/intel/esb6300/smbus.h b/src/southbridge/intel/esb6300/smbus.h
deleted file mode 100644
index 0a944d3..0000000
--- a/src/southbridge/intel/esb6300/smbus.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#include <device/smbus_def.h>
-
-#define SMBHSTSTAT 0x0
-#define SMBHSTCTL 0x2
-#define SMBHSTCMD 0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT 0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
-
-#define SMBUS_TIMEOUT (100*1000*10)
-
-#include <delay.h>
-
-static int smbus_wait_until_ready(unsigned smbus_io_base)
-{
- unsigned loops = SMBUS_TIMEOUT;
- unsigned char byte;
- do {
- udelay(100);
- if (--loops == 0)
- break;
- byte = inb(smbus_io_base + SMBHSTSTAT);
- } while(byte & 1);
- return loops?0:-1;
-}
-
-static int smbus_wait_until_done(unsigned smbus_io_base)
-{
- unsigned loops = SMBUS_TIMEOUT;
- unsigned char byte;
- do {
- udelay(100);
- if (--loops == 0)
- break;
- byte = inb(smbus_io_base + SMBHSTSTAT);
- } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
- return loops?0:-1;
-}
-
-static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
-{
- unsigned loops = SMBUS_TIMEOUT;
- unsigned char byte;
- do {
- udelay(100);
- if (--loops == 0)
- break;
- byte = inb(smbus_io_base + SMBHSTSTAT);
- } while((byte&(1<<7)) == 0);
- return loops?0:-1;
-}
-
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
-{
- unsigned char global_status_register;
- unsigned char byte;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
- /* setup transaction */
- /* disable interrupts */
- outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
- /* set the command/address... */
- outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
- /* set up for a byte data read */
- outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
- /* clear any lingering errors, so the transaction will run */
- outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
-
- /* clear the data byte...*/
- outb(0, smbus_io_base + SMBHSTDAT0);
-
- /* start the command */
- outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
-
- global_status_register = inb(smbus_io_base + SMBHSTSTAT);
-
- /* Ignore the In Use Status... */
- global_status_register &= ~(3 << 5);
-
- /* read results of transaction */
- byte = inb(smbus_io_base + SMBHSTDAT0);
- if (global_status_register != (1 << 1)) {
- return SMBUS_ERROR;
- }
- return byte;
-}
diff --git a/src/southbridge/intel/esb6300/uhci.c b/src/southbridge/intel/esb6300/uhci.c
deleted file mode 100644
index 0b65b01..0000000
--- a/src/southbridge/intel/esb6300/uhci.c
+++ /dev/null
@@ -1,56 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "esb6300.h"
-
-static void uhci_init(struct device *dev)
-{
- uint32_t cmd;
-
-#if 1
- printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
- cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
- cmd | PCI_COMMAND_MASTER);
-
-
- printk(BIOS_DEBUG, "done.\n");
-#endif
-
-}
-
-static struct pci_operations lops_pci = {
- /* The subsystem id follows the ide controller */
- .set_subsystem = 0,
-};
-
-static struct device_operations uhci_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = uhci_init,
- .scan_bus = 0,
- .enable = esb6300_enable,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver usb1_driver __pci_driver = {
- .ops = &uhci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_USB1,
-};
-
-static const struct pci_driver usb2_driver __pci_driver = {
- .ops = &uhci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_USB2,
-};
-
-/* Note: May or may not need different init than UHCI. */
-static const struct pci_driver ehci_driver __pci_driver = {
- .ops = &uhci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_6300ESB_EHCI,
-};
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