[coreboot-gerrit] Patch set updated for coreboot: pcengines/apu1: disable unused GPP CLK ports

[Felix Held (felix-coreboot@felixheld.de)]

Felix Held (felix-coreboot at felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12082

-gerrit

commit a9420487577b21cfea86d35b1e60dfd8a240ee65
Author: Felix Held <felix-coreboot at felixheld.de>
Date:   Sat Oct 17 14:34:41 2015 +0200

    pcengines/apu1: disable unused GPP CLK ports
    
    disabling unconnected clock outputs saves some power
    
    Change-Id: Ib3efebb8656392d58d762c23827168017d273de8
    Signed-off-by: Felix Held <felix-coreboot at felixheld.de>
---
 src/mainboard/pcengines/apu1/mainboard.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index 7d50c66..832cb89 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -187,6 +187,18 @@ static void mainboard_enable(device_t dev)
 
 	config_gpio_mux();
 
+	/* Power off unused clock pins of GPP PCIe devices */
+	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
+	/* GPP CLK0-2 are connected to the 3 ethernet chips
+	 * GPP CLK3-4 are connected to the miniPCIe slots
+	 * GPP CLK5 is connected to test pads */
+	write8(misc_mem_clk_cntrl + 0, 0xFF);
+	write8(misc_mem_clk_cntrl + 1, 0xFF);
+	write8(misc_mem_clk_cntrl + 2, 0xFF);
+	/* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */
+	write8(misc_mem_clk_cntrl + 3, 0x00);
+	write8(misc_mem_clk_cntrl + 4, 0x00);
+
 	/* Initialize the PIRQ data structures for consumption */
 	pirq_setup();
 }