[coreboot-gerrit] New patch to review for coreboot: amd/sb700: clean up recommended changes

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12206

-gerrit

commit 212318e53767251f519158304c9cd14917bd5d58
Author: Martin Roth <martinroth at google.com>
Date:   Tue Oct 27 14:10:22 2015 -0600

    amd/sb700: clean up recommended changes
    
    This patch addresses changes requested to commit 85c39a4c
    - remove unused/commented out code
    - remove unnecessary guards around acpi_get_sleep_type()
    
    Change-Id: I2878e038d2f9f8d182615e1f4a75ddce5c45d5f3
    Signed-off-by: Martin Roth <martinroth at google.com>
---
 src/southbridge/amd/sb700/early_setup.c | 6 ------
 src/southbridge/amd/sb700/lpc.c         | 2 --
 2 files changed, 8 deletions(-)

diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 4a3a5a8..737b3b8 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -621,12 +621,6 @@ static void sb700_pmio_por_init(void)
 	byte |= 1 << 0;
 	pmio_write(0xB2, byte);
 
-	// FIXME: Enabling this causes boot to hang while initializing processors.
-// 	/* Enable automatic C1e state switch */
-// 	byte = pmio_read(0xc9);
-// 	byte |= 0x11;
-// 	pmio_write(0xc9, byte);
-
 	/* Enable precision HPET clock and automatic C state switch */
 	byte = pmio_read(0xbb);
 	byte |= 0xc0;
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 145a01f..8f286d7 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -87,13 +87,11 @@ static void lpc_init(device_t dev)
 	cmos_check_update_date();
 }
 
-#if (!IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
 int acpi_get_sleep_type(void)
 {
 	u16 tmp = inw(ACPI_PM1_CNT_BLK);
 	return ((tmp & (7 << 10)) >> 10);
 }
-#endif
 
 #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
 void backup_top_of_ram(uint64_t ramtop)