[coreboot-gerrit] Patch set updated for coreboot: cpu/intel/fsp_model_206ax: Load microcode in coreboot
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Mon Oct 26 18:29:21 CET 2015
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12196
-gerrit
commit 02e0e26713e92e96c77c87d046c63bd26acd0871
Author: Martin Roth <martinroth at google.com>
Date: Mon Oct 26 10:07:24 2015 -0600
cpu/intel/fsp_model_206ax: Load microcode in coreboot
Intel's FSP 1.0 platforms are moving back to loading microcode in
coreboot instead of in the FSP. Update the Ivy Bridge chips to
be compatible.
Change-Id: I4af155dea51e89ab9595b922c95ceade29a2dc52
Signed-off-by: Martin Roth <martinroth at google.com>
---
src/cpu/intel/fsp_model_206ax/Kconfig | 7 +------
src/cpu/intel/fsp_model_206ax/bootblock.c | 2 ++
src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 3 +++
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 606000e..a1b3d71 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -37,7 +37,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
- select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN
+ select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER
@@ -54,9 +54,4 @@ config ENABLE_VMX
bool "Enable VMX for virtualization"
default n
-config CPU_MICROCODE_CBFS_LOC
- hex
- depends on SUPPORT_CPU_UCODE_IN_CBFS
- default 0xfff70000
-
endif
diff --git a/src/cpu/intel/fsp_model_206ax/bootblock.c b/src/cpu/intel/fsp_model_206ax/bootblock.c
index 28cbd7e..5543347 100644
--- a/src/cpu/intel/fsp_model_206ax/bootblock.c
+++ b/src/cpu/intel/fsp_model_206ax/bootblock.c
@@ -24,8 +24,10 @@
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
+#include <cpu/intel/microcode/microcode.c>
#include "model_206ax.h"
static void bootblock_cpu_init(void)
{
+ intel_update_microcode_from_cbfs();
}
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
index 9b76c22..cfe75b4 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
@@ -27,6 +27,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <cpu/x86/cache.h>
@@ -374,6 +375,8 @@ static void model_206ax_init(struct device *cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();
+ intel_update_microcode_from_cbfs();
+
/* Clear out pending MCEs */
configure_mca();
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