[coreboot-gerrit] New patch to review for coreboot: device/pci_device: Set bridge primary bus number before scanning

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12186

-gerrit

commit 1b93f7bcdff30528361988a90ae18fb1b25175b1
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Sat Oct 24 20:34:57 2015 -0500

    device/pci_device: Set bridge primary bus number before scanning
    
    Certain devices, such as the Intel 82575GB, contain multiple nested
    PCIe bridges (for example the PES12N3A).  Coreboot does not set
    the primary bus number of the lower bridges, causing upstream
    forwarding failure.  This in turn causes coreboot to fail to find
    the lowest devices (in this case the NICs), and as a result the
    required resources are not allocated and the NICs do not function.
    
    Change-Id: I4fd3aa21a04dbe89ac6a5995e7707af914d432b1
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/device/pci_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index cf2f74f..5123229 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1180,6 +1180,7 @@ static void pci_bridge_route(struct bus *link, scan_state state)
 	if (state == PCI_ROUTE_CLOSE) {
 		buses |= 0xfeff << 8;
 	} else if (state == PCI_ROUTE_SCAN) {
+		buses |= parent->secondary & 0xff;
 		buses |= ((u32) link->secondary & 0xff) << 8;
 		buses |= 0xff << 16; /* MAX PCI_BUS number here */
 	} else if (state == PCI_ROUTE_FINAL) {