[coreboot-gerrit] Patch merged into coreboot/master: southbridge/amd/sr5650: Add optional delay after link training

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 5a0efd255da0dbba2e6ff4b8ad9ca9bad8370857
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Fri Jun 12 20:08:29 2015 -0500

    southbridge/amd/sr5650: Add optional delay after link training
    
    Certain devices (such as the LSI SAS 2008 controller) do not
    respond to PCI probes immediately after link training.  If it
    is known that such a device is likely to be installed allow the
    mainboard to insert an appropriate delay.
    
    Change-Id: Ibcd9426628cacd6f88e6e3fcbc2b3eb7e3a92081
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
    Reviewed-on: http://review.coreboot.org/11991
    Reviewed-by: Edward O'Callaghan <edward.ocallaghan at koparo.com>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/11991 for details.

-gerrit