[coreboot-gerrit] New patch to review for coreboot: superio/intel: Add i8900 device
Marc Jones (marc@marcjonesconsulting.com)
gerrit at coreboot.org
Fri Oct 23 19:33:35 CEST 2015
Marc Jones (marc at marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12169
-gerrit
commit f1df14a2faff70ff2ee21d737b3ce34fd0e2496b
Author: Marc Jones <marc.jones at se-eng.com>
Date: Wed Sep 23 16:19:11 2015 -0600
superio/intel: Add i8900 device
The Intel i8900 Super I/O is similar to the previously
supported i3100.
Change-Id: I9a5b651cab35991c3c3e09fc4668d35ca2d221ba
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
src/superio/intel/Kconfig | 3 ++
src/superio/intel/Makefile.inc | 1 +
src/superio/intel/i8900/Makefile.inc | 22 +++++++++
src/superio/intel/i8900/early_serial.c | 69 ++++++++++++++++++++++++++
src/superio/intel/i8900/i8900.h | 60 +++++++++++++++++++++++
src/superio/intel/i8900/superio.c | 90 ++++++++++++++++++++++++++++++++++
6 files changed, 245 insertions(+)
diff --git a/src/superio/intel/Kconfig b/src/superio/intel/Kconfig
index 606f92a..464aa44 100644
--- a/src/superio/intel/Kconfig
+++ b/src/superio/intel/Kconfig
@@ -19,3 +19,6 @@
config SUPERIO_INTEL_I3100
bool
+
+config SUPERIO_INTEL_I8900
+ bool
diff --git a/src/superio/intel/Makefile.inc b/src/superio/intel/Makefile.inc
index 193c717..da275ab 100644
--- a/src/superio/intel/Makefile.inc
+++ b/src/superio/intel/Makefile.inc
@@ -18,3 +18,4 @@
##
subdirs-y += i3100
+subdirs-y += i8900
diff --git a/src/superio/intel/i8900/Makefile.inc b/src/superio/intel/i8900/Makefile.inc
new file mode 100644
index 0000000..abdc473
--- /dev/null
+++ b/src/superio/intel/i8900/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Arastra, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+romstage-$(CONFIG_SUPERIO_INTEL_I8900) += early_serial.c
+ramstage-$(CONFIG_SUPERIO_INTEL_I8900) += superio.c
diff --git a/src/superio/intel/i8900/early_serial.c b/src/superio/intel/i8900/early_serial.c
new file mode 100644
index 0000000..fb211e9
--- /dev/null
+++ b/src/superio/intel/i8900/early_serial.c
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include "i8900.h"
+
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0x80, port);
+ outb(0x86, port);
+}
+
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0x68, port);
+ outb(0x08, port);
+}
+
+/* Enable device interrupts, set UART_CLK predivide. */
+void i8900_configure_uart_clk(pnp_devfn_t dev, u8 predivide)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_write_config(dev, I8900_SIW_CONFIGURATION,
+ (predivide << 2) | I8900_ENABLE_SIRQ);
+ pnp_exit_ext_func_mode(dev);
+}
+
+void i8900_enable_serial(pnp_devfn_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+
+void i8900_enable_wdt(pnp_devfn_t dev, u16 iobase)
+{
+ /* Enable WDT */
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
diff --git a/src/superio/intel/i8900/i8900.h b/src/superio/intel/i8900/i8900.h
new file mode 100644
index 0000000..e53a0a8
--- /dev/null
+++ b/src/superio/intel/i8900/i8900.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_INTEL_I8900_I8900_H
+#define SUPERIO_INTEL_I8900_I8900_H
+
+/*
+ * The SIW ("Serial I/O and Watchdog Timer") integrated into the i8900 is
+ * very similar to a Super I/O, both in functionality and config mechanism.
+ *
+ * The SIW contains:
+ * - UART(s)
+ * - Serial interrupt controller
+ * - Watchdog timer (WDT)
+ * - LPC interface
+ */
+
+/* Logical device numbers (LDNs). */
+#define I8900_SP1 0x04 /* Com1 */
+#define I8900_SP2 0x05 /* Com2 */
+#define I8900_WDT 0x06 /* Watchdog timer */
+
+/* Registers and bit definitions: */
+
+#define I8900_SIW_CONFIGURATION 0x29
+
+/*
+ * SIW_CONFIGURATION[3:2] = UART_CLK predivide
+ * 00: divide by 1
+ * 01: divide by 8
+ * 10: divide by 26
+ * 11: reserved
+ */
+#define I8900_UART_CLK_PREDIVIDE_1 0x00
+#define I8900_UART_CLK_PREDIVIDE_8 0x01
+#define I8900_UART_CLK_PREDIVIDE_26 0x02
+#define I8900_ENABLE_SIRQ 0x01
+
+void i8900_configure_uart_clk(device_t dev, u8 predivide);
+void i8900_enable_serial(device_t dev, u16 iobase);
+void i8900_enable_wdt(device_t dev, u16 iobase);
+
+#endif
diff --git a/src/superio/intel/i8900/superio.c b/src/superio/intel/i8900/superio.c
new file mode 100644
index 0000000..f92f457
--- /dev/null
+++ b/src/superio/intel/i8900/superio.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stdlib.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <drivers/uart/uart8250reg.h>
+#include "i8900.h"
+#include <arch/io.h>
+
+static void pnp_enter_ext_func_mode(struct device *dev)
+{
+ outb(0x80, dev->path.pnp.port);
+ outb(0x86, dev->path.pnp.port);
+}
+
+static void pnp_exit_ext_func_mode(struct device *dev)
+{
+ outb(0x68, dev->path.pnp.port);
+ outb(0x08, dev->path.pnp.port);
+}
+
+static void i8900_init(struct device *dev)
+{
+ if (!dev->enabled)
+ return;
+}
+
+static void i8900_pnp_set_resources(struct device *dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_resources(dev);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void i8900_pnp_enable_resources(struct device *dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_enable_resources(dev);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void i8900_pnp_enable(struct device *dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, !!dev->enabled);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = i8900_pnp_set_resources,
+ .enable_resources = i8900_pnp_enable_resources,
+ .enable = i8900_pnp_enable,
+ .init = i8900_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, I8900_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, I8900_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, I8900_WDT, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_intel_i8900_ops = {
+ CHIP_NAME("Intel 8900 Super I/O")
+ .enable_dev = enable_dev,
+};
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