[coreboot-gerrit] New patch to review for coreboot: google/glados: csme: program sml gpios for csme power gating

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12160

-gerrit

commit 4a0a41c54a3edbe661f88956dfef8955796c2cd4
Author: Archana Patni <archana.patni at intel.com>
Date:   Thu Oct 8 01:43:47 2015 +0530

    google/glados: csme: program sml gpios for csme power gating
    
    For SMT controllers to power gate, all SMT/SMS clock, data and alert signals should be inactive.
    
    The SML0 blocks are not used for any functional purposes and are not configured in the GPIO tables.
    SMT hardware will not allow the blocks to be power gated in this scenario. The SML* pins are
    now configured as GPIOs - input and deep.
    
    With this change, the SMT blocks are properly power gating.
    
    BRANCH=none
    BUG=chrome-os-partner:45618
    TEST=build for Glados.
    
    Change-Id: Ie5406f2a1e0c485ac1290e2154755085fa3bb7b9
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5b3fe3c2ddea4c5daedb04078b24cff14efa49d5
    Original-Change-Id: I8dcc0bfc121e612a174e6fe3152650d0fcd68f39
    Original-Signed-off-by: Archana Patni <archana.patni at intel.com>
    Original-Signed-off-by: Subramony Sesha <subramony.sesha at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/306481
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/gpio.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
index c3d0835..0d335c5 100644
--- a/src/mainboard/google/glados/gpio.h
+++ b/src/mainboard/google/glados/gpio.h
@@ -100,15 +100,15 @@ static const struct pad_config gpio_table[] = {
 /* GSPI1_CLK */		/* GPP_B20 */
 /* GSPI1_MISO */	/* GPP_B21 */
 /* GSPI1_MOSI */	/* GPP_B22 */
-/* SM1ALERT# */		/* GPP_B23 */
+/* SM1ALERT# */		PAD_CFG_GPO(GPP_B23, 0, DEEP),
 /* SMBCLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
 /* SMBDATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
 /* SMBALERT# */		/* GPP_C2 */
-/* SML0CLK */		/* GPP_C3 */
-/* SML0DATA */		/* GPP_C4 */
-/* SML0ALERT# */	/* GPP_C5 */
+/* SML0CLK */		PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+/* SML0DATA */		PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+/* SML0ALERT# */	PAD_CFG_GPO(GPP_C5, 0, DEEP),
 /* SM1CLK */		PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
-/* SM1DATA */		/* GPP_C7 */
+/* SM1DATA */		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
 /* UART0_RXD */		/* GPP_C8 */
 /* UART0_TXD */		/* GPP_C9 */
 /* UART0_RTS# */	/* GPP_C10 */