[coreboot-gerrit] New patch to review for coreboot: FSP 1.1: Move common FSP code
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Oct 23 13:26:02 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12156
-gerrit
commit fdc138e15c7f834e68652bf2e2537ec9c4fd7909
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Thu Oct 15 12:07:03 2015 -0700
FSP 1.1: Move common FSP code
Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values
associated with this common code.
BRANCH=none
BUG=None
TEST=Build and run on kunimitsu
Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy at intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy at intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/drivers/intel/fsp1_1/Kconfig | 21 ++
src/drivers/intel/fsp1_1/Makefile.inc | 7 +
src/drivers/intel/fsp1_1/fsp_util.c | 46 +++
src/drivers/intel/fsp1_1/include/fsp/gma.h | 182 +++++++++++
src/drivers/intel/fsp1_1/include/fsp/gop.h | 2 +-
src/drivers/intel/fsp1_1/include/fsp/memmap.h | 51 +++
src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 39 +++
src/drivers/intel/fsp1_1/include/fsp/romstage.h | 95 ++++++
src/drivers/intel/fsp1_1/include/fsp/stack.h | 35 ++
src/drivers/intel/fsp1_1/include/fsp/util.h | 2 +
src/drivers/intel/fsp1_1/raminit.c | 317 ++++++++++++++++++
src/drivers/intel/fsp1_1/ramstage.c | 219 +++++++++++++
src/drivers/intel/fsp1_1/romstage.c | 413 +++++++++++++++++++++++
src/drivers/intel/fsp1_1/stack.c | 183 +++++++++++
src/drivers/intel/fsp1_1/stage_cache.c | 32 ++
src/drivers/intel/fsp1_1/vbt.c | 51 +++
src/soc/intel/braswell/Kconfig | 8 +-
src/soc/intel/braswell/cpu.c | 2 +-
src/soc/intel/braswell/include/soc/acpi.h | 2 +-
src/soc/intel/braswell/include/soc/ramstage.h | 2 +-
src/soc/intel/braswell/include/soc/romstage.h | 2 +-
src/soc/intel/braswell/memmap.c | 2 +-
src/soc/intel/braswell/northcluster.c | 2 +-
src/soc/intel/braswell/ramstage.c | 1 -
src/soc/intel/common/Kconfig | 25 --
src/soc/intel/common/Makefile.inc | 11 +-
src/soc/intel/common/fsp_ramstage.c | 219 -------------
src/soc/intel/common/gma.h | 182 -----------
src/soc/intel/common/memmap.h | 51 ---
src/soc/intel/common/raminit.c | 317 ------------------
src/soc/intel/common/ramstage.h | 39 ---
src/soc/intel/common/romstage.c | 416 ------------------------
src/soc/intel/common/romstage.h | 95 ------
src/soc/intel/common/stack.c | 183 -----------
src/soc/intel/common/stack.h | 35 --
src/soc/intel/common/stage_cache.c | 32 --
src/soc/intel/common/util.c | 46 ---
src/soc/intel/common/util.h | 2 -
src/soc/intel/common/vbt.c | 51 ---
src/soc/intel/skylake/Kconfig | 8 +-
src/soc/intel/skylake/include/soc/ramstage.h | 2 +-
src/soc/intel/skylake/include/soc/romstage.h | 2 +-
src/soc/intel/skylake/include/soc/smm.h | 4 +-
src/soc/intel/skylake/ramstage.c | 1 -
44 files changed, 1714 insertions(+), 1723 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index d23d966..d068337 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -116,6 +116,22 @@ config DISPLAY_UPD_DATA
Display the user specified product data prior to memory
initialization.
+config FSP_RAM_INIT
+ bool
+ default n
+
+config FSP_ROMSTAGE
+ bool
+ default n
+
+config FSP_STACK
+ bool
+ default n
+
+config FSP_STAGE_CACHE
+ bool
+ default n
+
config FSP_USES_UPD
bool
default n
@@ -127,6 +143,11 @@ config GOP_SUPPORT
bool "Enable GOP support"
default y
+config ROMSTAGE_RAM_STACK_SIZE
+ hex "Size of the romstage RAM stack in bytes"
+ default 0x5000
+ depends on FSP_STACK
+
config USE_GENERIC_FSP_CAR_INC
bool
default n
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index a90e23a..19bee82 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -25,12 +25,19 @@ verstage-y += verstage.c
romstage-y += car.c
romstage-y += fsp_util.c
romstage-y += hob.c
+romstage-$(CONFIG_FSP_RAM_INIT) += raminit.c
+romstage-$(CONFIG_FSP_ROMSTAGE) += romstage.c
romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
+romstage-$(CONFIG_FSP_STACK) += stack.c
+romstage-$(CONFIG_FSP_STAGE_CACHE) += stage_cache.c
ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
ramstage-y += fsp_relocate.c
ramstage-y += fsp_util.c
ramstage-y += hob.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_FSP_STAGE_CACHE) += stage_cache.c
+ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
# Where FspUpdVpd.h can be picked up from.
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index d44f0f0..3b42c16 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -248,3 +248,49 @@ void fsp_update_fih(FSP_INFO_HEADER *fih)
fspr->fih = (uintptr_t)fih;
}
+
+void soc_display_upd_value(const char *name, uint32_t size, uint64_t old,
+ uint64_t new)
+{
+ if (old == new) {
+ switch (size) {
+ case 1:
+ printk(BIOS_SPEW, " 0x%02llx: %s\n", new, name);
+ break;
+
+ case 2:
+ printk(BIOS_SPEW, " 0x%04llx: %s\n", new, name);
+ break;
+
+ case 4:
+ printk(BIOS_SPEW, " 0x%08llx: %s\n", new, name);
+ break;
+
+ case 8:
+ printk(BIOS_SPEW, " 0x%016llx: %s\n", new, name);
+ break;
+ }
+ } else {
+ switch (size) {
+ case 1:
+ printk(BIOS_SPEW, " 0x%02llx --> 0x%02llx: %s\n", old,
+ new, name);
+ break;
+
+ case 2:
+ printk(BIOS_SPEW, " 0x%04llx --> 0x%04llx: %s\n", old,
+ new, name);
+ break;
+
+ case 4:
+ printk(BIOS_SPEW, " 0x%08llx --> 0x%08llx: %s\n", old,
+ new, name);
+ break;
+
+ case 8:
+ printk(BIOS_SPEW, " 0x%016llx --> 0x%016llx: %s\n",
+ old, new, name);
+ break;
+ }
+ }
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gma.h b/src/drivers/intel/fsp1_1/include/fsp/gma.h
new file mode 100644
index 0000000..64b2a28
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/gma.h
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _GMA_H_
+#define _GMA_H_
+
+#include <types.h>
+
+/* IGD PCI Configuration register */
+#define ASLS 0xfc /* OpRegion Base */
+#define SWSCI 0xe8 /* SWSCI Register */
+#define GSSCIE (1 << 0) /* SCI Event trigger */
+#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */
+
+/* mailbox 0: header */
+typedef struct {
+ u8 signature[16];
+ u32 size;
+ u32 version;
+ u8 sbios_version[32];
+ u8 vbios_version[16];
+ u8 driver_version[16];
+ u32 mailboxes;
+ u8 reserved[164];
+} __attribute__((packed)) opregion_header_t;
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION 2
+
+#define IGD_MBOX1 (1 << 0)
+#define IGD_MBOX2 (1 << 1)
+#define IGD_MBOX3 (1 << 2)
+#define IGD_MBOX4 (1 << 3)
+#define IGD_MBOX5 (1 << 4)
+
+#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+ IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public acpi methods */
+typedef struct {
+ u32 drdy;
+ u32 csts;
+ u32 cevt;
+ u8 reserved1[20];
+ u32 didl[8];
+ u32 cpdl[8];
+ u32 cadl[8];
+ u32 nadl[8];
+ u32 aslp;
+ u32 tidx;
+ u32 chpd;
+ u32 clid;
+ u32 cdck;
+ u32 sxsw;
+ u32 evts;
+ u32 cnot;
+ u32 nrdy;
+ u8 reserved2[60];
+} __attribute__((packed)) opregion_mailbox1_t;
+
+/* mailbox 2: software sci interface */
+typedef struct {
+ u32 scic;
+ u32 parm;
+ u32 dslp;
+ u8 reserved[244];
+} __attribute__((packed)) opregion_mailbox2_t;
+
+/* mailbox 3: power conservation */
+typedef struct {
+ u32 ardy;
+ u32 aslc;
+ u32 tche;
+ u32 alsi;
+ u32 bclp;
+ u32 pfit;
+ u32 cblv;
+ u16 bclm[20];
+ u32 cpfm;
+ u32 epfm;
+ u8 plut[74];
+ u32 pfmb;
+ u32 ccdv;
+ u32 pcft;
+ u8 reserved[94];
+} __attribute__((packed)) opregion_mailbox3_t;
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID (1 << 31)
+#define IGD_WORD_FIELD_VALID (1 << 15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+typedef struct {
+ u8 gvd1[7168];
+} __attribute__((packed)) opregion_vbt_t;
+
+/* IGD OpRegion */
+typedef struct {
+ opregion_header_t header;
+ opregion_mailbox1_t mailbox1;
+ opregion_mailbox2_t mailbox2;
+ opregion_mailbox3_t mailbox3;
+ opregion_vbt_t vbt;
+} __attribute__((packed)) igd_opregion_t;
+
+/* Intel Video BIOS (Option ROM) */
+typedef struct {
+ u16 signature;
+ u8 size;
+ u8 reserved[21];
+ u16 pcir_offset;
+ u16 vbt_offset;
+} __attribute__((packed)) optionrom_header_t;
+
+#define OPROM_SIGNATURE 0xaa55
+
+typedef struct {
+ u32 signature;
+ u16 vendor;
+ u16 device;
+ u16 reserved1;
+ u16 length;
+ u8 revision;
+ u8 classcode[3];
+ u16 imagelength;
+ u16 coderevision;
+ u8 codetype;
+ u8 indicator;
+ u16 reserved2;
+} __attribute__((packed)) optionrom_pcir_t;
+
+typedef struct {
+ u8 hdr_signature[20];
+ u16 hdr_version;
+ u16 hdr_size;
+ u16 hdr_vbt_size;
+ u8 hdr_vbt_checksum;
+ u8 hdr_reserved;
+ u32 hdr_vbt_datablock;
+ u32 hdr_aim[4];
+ u8 datahdr_signature[16];
+ u16 datahdr_version;
+ u16 datahdr_size;
+ u16 datahdr_datablocksize;
+ u8 coreblock_id;
+ u16 coreblock_size;
+ u16 coreblock_biossize;
+ u8 coreblock_biostype;
+ u8 coreblock_releasestatus;
+ u8 coreblock_hwsupported;
+ u8 coreblock_integratedhw;
+ u8 coreblock_biosbuild[4];
+ u8 coreblock_biossignon[155];
+} __attribute__((packed)) optionrom_vbt_t;
+
+#define VBT_SIGNATURE 0x54425624
+
+#endif /* _GMA_H_ */
+
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h
index 78d2878..14fafd7 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/gop.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/gop.h
@@ -23,7 +23,7 @@
/* GOP support */
#if IS_ENABLED(CONFIG_GOP_SUPPORT)
-#include <soc/intel/common/gma.h>
+#include <fsp/gma.h>
const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h
new file mode 100644
index 0000000..3d51539
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/memmap.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _COMMON_MEMMAP_H_
+#define _COMMON_MEMMAP_H_
+
+#include <types.h>
+
+/*
+ * mmap_region_granluarity must to return a size which is a positive non-zero
+ * integer multiple of the SMM size when SMM is in use. When not using SMM,
+ * this value should be set to 8 MiB.
+ */
+size_t mmap_region_granluarity(void);
+
+/* Fills in the arguments for the entire SMM region covered by chipset
+ * protections. e.g. TSEG. */
+void smm_region(void **start, size_t *size);
+
+enum {
+ /* SMM handler area. */
+ SMM_SUBREGION_HANDLER,
+ /* SMM cache region. */
+ SMM_SUBREGION_CACHE,
+ /* Chipset specific area. */
+ SMM_SUBREGION_CHIPSET,
+ /* Total sub regions supported. */
+ SMM_SUBREGION_NUM,
+};
+
+/* Fills in the start and size for the requested SMM subregion. Returns
+ * 0 on susccess, < 0 on failure. */
+int smm_subregion(int sub, void **start, size_t *size);
+
+#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
new file mode 100644
index 0000000..d6cb895
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _INTEL_COMMON_RAMSTAGE_H_
+#define _INTEL_COMMON_RAMSTAGE_H_
+
+#include <fsp/util.h>
+#include <soc/intel/common/util.h>
+#include <stdint.h>
+
+/* Perform Intel silicon init. */
+void intel_silicon_init(void);
+/* Called after the silicon init code has run. */
+void soc_after_silicon_init(void);
+/* Initialize UPD data before SiliconInit call. */
+void soc_silicon_init_params(SILICON_INIT_UPD *params);
+void mainboard_silicon_init_params(SILICON_INIT_UPD *params);
+void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
+ SILICON_INIT_UPD *new);
+void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params);
+
+#endif /* _INTEL_COMMON_RAMSTAGE_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
new file mode 100644
index 0000000..272679f
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _COMMON_ROMSTAGE_H_
+#define _COMMON_ROMSTAGE_H_
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <memory_info.h>
+#include <fsp/car.h>
+#include <fsp/util.h>
+#include <soc/intel/common/util.h>
+#include <soc/pei_data.h>
+#include <soc/pm.h> /* chip_power_state */
+
+struct romstage_params {
+ unsigned long bist;
+ struct chipset_power_state *power_state;
+ struct pei_data *pei_data;
+ void *chipset_context;
+};
+
+/*
+ * FSP Boot Flow:
+ * 1. src/cpu/x86/16bit/reset.inc
+ * 2. src/cpu/x86/16bit/entry.inc
+ * 3. other modules
+ * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc
+ * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp
+ * 6. FSP binary/TempRamInit
+ * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return
+ * 8. src/soc/intel/common/romstage.c/romstage_main
+ * 9 src/soc/.../romstage/.../soc_pre_console_init
+ * 10 src/console/console.c/console_init
+ * 11 src/soc/.../romstage/.../soc_romstage_init
+ * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry
+ * 13. src/soc/intel/common/romstage.c/romstage_common
+ * 14 src/soc/.../romstage/.../soc_pre_raminit
+ * 15. FSP binary/MemoryInit
+ * 16. src/soc/intel/common/romstage.c/romstage_common - return
+ * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return
+ * 18. src/soc/intel/common/romstage.c/romstage_main - return
+ * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs
+ * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup
+ * after call to romstage_main
+ * 21. FSP binary/TempRamExit
+ * 22. src/soc/intel/common/romstage.c/romstage_after_car
+ * 23. FSP binary/SiliconInit
+ * 24. src/soc/intel/common/romstage.c/romstage_after_car - return
+ * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
+ * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
+ * 27. FSP binary/FspNotify
+ * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
+ * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
+ * 30. FSP binary/FspNotify
+ */
+
+void mainboard_check_ec_image(struct romstage_params *params);
+void mainboard_memory_init_params(struct romstage_params *params,
+ MEMORY_INIT_UPD *memory_params);
+void mainboard_romstage_entry(struct romstage_params *params);
+void mainboard_save_dimm_info(struct romstage_params *params);
+void mainboard_add_dimm_info(struct romstage_params *params,
+ struct memory_info *mem_info,
+ int channel, int dimm, int index);
+void raminit(struct romstage_params *params);
+void report_memory_config(void);
+void romstage_common(struct romstage_params *params);
+asmlinkage void *romstage_main(FSP_INFO_HEADER *fih);
+void *setup_stack_and_mtrrs(void);
+void soc_after_ram_init(struct romstage_params *params);
+void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
+ MEMORY_INIT_UPD *new);
+void soc_memory_init_params(struct romstage_params *params,
+ MEMORY_INIT_UPD *upd);
+void soc_pre_ram_init(struct romstage_params *params);
+
+#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/stack.h b/src/drivers/intel/fsp1_1/include/fsp/stack.h
new file mode 100644
index 0000000..f5333a7
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/stack.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _COMMON_STACK_H_
+#define _COMMON_STACK_H_
+
+#include <stdint.h>
+
+static inline void *stack_push32(void *stack, uint32_t value)
+{
+ uint32_t *stack32 = stack;
+
+ stack32 = &stack32[-1];
+ *stack32 = value;
+ return stack32;
+}
+
+#endif /* _COMMON_STACK_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index b3772a2..2905e59 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -46,6 +46,8 @@ void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
const void *hob_start);
void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
void *get_first_resource_hob(const EFI_GUID *guid);
+void soc_display_upd_value(const char *name, uint32_t size, uint64_t old,
+ uint64_t new);
/*
* Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success.
* The FSP source is pointed to by region_device and the relocation information
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
new file mode 100644
index 0000000..865452e
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -0,0 +1,317 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014-2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/memmap.h>
+#include <fsp/util.h>
+#include <lib.h> /* hexdump */
+#include <reset.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <string.h>
+#include <timestamp.h>
+
+void raminit(struct romstage_params *params)
+{
+ const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
+ EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
+ FSP_INFO_HEADER *fsp_header;
+ EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory;
+ FSP_MEMORY_INIT fsp_memory_init;
+ FSP_MEMORY_INIT_PARAMS fsp_memory_init_params;
+ const EFI_GUID fsp_reserved_guid =
+ FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
+ void *fsp_reserved_memory_area;
+ FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer;
+ void *hob_list_ptr;
+ FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
+ const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
+ MEMORY_INIT_UPD memory_init_params;
+ const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+ u32 *mrc_hob;
+ u32 fsp_reserved_bytes;
+ MEMORY_INIT_UPD *original_params;
+ struct pei_data *pei_ptr;
+ EFI_STATUS status;
+ VPD_DATA_REGION *vpd_ptr;
+ UPD_DATA_REGION *upd_ptr;
+ int fsp_verification_failure = 0;
+#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+ unsigned long int data;
+ EFI_PEI_HOB_POINTERS hob_ptr;
+#endif
+
+ /*
+ * Find and copy the UPD region to the stack so the platform can modify
+ * the settings if needed. Modifications to the UPD buffer are done in
+ * the platform callback code. The platform callback code is also
+ * responsible for assigning the UpdDataRngPtr to this buffer if any
+ * updates are made. The default state is to leave the UpdDataRngPtr
+ * set to NULL. This indicates that the FSP code will use the UPD
+ * region in the FSP binary.
+ */
+ post_code(0x34);
+ fsp_header = params->chipset_context;
+ vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
+ fsp_header->ImageBase);
+ printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
+ upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
+ fsp_header->ImageBase);
+ printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr);
+ original_params = (void *)((u8 *)upd_ptr +
+ upd_ptr->MemoryInitUpdOffset);
+ memcpy(&memory_init_params, original_params,
+ sizeof(memory_init_params));
+
+ /* Zero fill RT Buffer data and start populating fields. */
+ memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
+ pei_ptr = params->pei_data;
+ if (pei_ptr->boot_mode == SLEEP_STATE_S3) {
+ fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
+ } else if (pei_ptr->saved_data != NULL) {
+ fsp_rt_common_buffer.BootMode =
+ BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
+ } else {
+ fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION;
+ }
+ fsp_rt_common_buffer.UpdDataRgnPtr = &memory_init_params;
+ fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size();
+
+ /* Get any board specific changes */
+ fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data;
+ fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer;
+ fsp_memory_init_params.HobListPtr = &hob_list_ptr;
+
+ /* Update the UPD data */
+ soc_memory_init_params(params, &memory_init_params);
+ mainboard_memory_init_params(params, &memory_init_params);
+ post_code(0x36);
+
+ /* Display the UPD data */
+ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
+ soc_display_memory_init_params(original_params,
+ &memory_init_params);
+
+ /* Call FspMemoryInit to initialize RAM */
+ fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase
+ + fsp_header->FspMemoryInitEntryOffset);
+ printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init);
+ printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n",
+ fsp_memory_init_params.NvsBufferPtr);
+ printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n",
+ fsp_memory_init_params.RtBufferPtr);
+ printk(BIOS_SPEW, " 0x%p: HobListPtr\n",
+ fsp_memory_init_params.HobListPtr);
+
+ timestamp_add_now(TS_FSP_MEMORY_INIT_START);
+ status = fsp_memory_init(&fsp_memory_init_params);
+ post_code(0x37);
+ timestamp_add_now(TS_FSP_MEMORY_INIT_END);
+
+ printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+ if (status != EFI_SUCCESS)
+ die("ERROR - FspMemoryInit failed to initialize memory!\n");
+
+ /* Locate the FSP reserved memory area */
+ fsp_reserved_bytes = 0;
+ fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr);
+ if (fsp_memory == NULL) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG,
+ "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n");
+ } else {
+ fsp_reserved_bytes = fsp_memory->ResourceLength;
+ printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n",
+ (unsigned long int)fsp_reserved_bytes);
+ }
+
+ /* Display SMM area */
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ char *smm_base;
+ size_t smm_size;
+
+ smm_region((void **)&smm_base, &smm_size);
+ printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size);
+ printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base);
+#endif
+
+ /* Migrate CAR data */
+ printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
+ if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
+ cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+ fsp_reserved_bytes);
+ } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+ fsp_reserved_bytes)) {
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+ printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ hard_reset();
+#endif
+ }
+
+ /* Save the FSP runtime parameters. */
+ fsp_set_runtime(fsp_header, hob_list_ptr);
+
+ /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */
+ cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr);
+ if (cbmem_root == NULL) {
+ fsp_verification_failure = 1;
+ printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n");
+ printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n",
+ fsp_rt_common_buffer.BootLoaderTolumSize);
+ }
+
+ /* Locate the FSP_SMBIOS_MEMORY_INFO HOB */
+ memory_info_hob = get_next_guid_hob(&memory_info_hob_guid,
+ hob_list_ptr);
+ if (NULL == memory_info_hob) {
+ printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n");
+ fsp_verification_failure = 1;
+ } else {
+ printk(BIOS_DEBUG,
+ "FSP_SMBIOS_MEMORY_INFO HOB: 0x%p\n",
+ memory_info_hob);
+ }
+
+#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+ if (hob_list_ptr == NULL)
+ die("ERROR - HOB pointer is NULL!\n");
+
+ /*
+ * Verify that FSP is generating the required HOBs:
+ * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
+ * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified above
+ * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified below
+ * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified above
+ * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit
+ * FSP_SMBIOS_MEMORY_INFO HOB verified above
+ */
+ if (NULL != cbmem_root) {
+ printk(BIOS_DEBUG,
+ "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n",
+ cbmem_root);
+ data = cbmem_root->PhysicalStart;
+ printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
+ data = cbmem_root->ResourceLength;
+ printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
+ }
+ hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
+ if (NULL == hob_ptr.Raw) {
+ printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
+ fsp_verification_failure =
+ (params->pei_data->saved_data == NULL) ? 1 : 0;
+ } else {
+ printk(BIOS_DEBUG,
+ "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n",
+ hob_ptr.Raw);
+ }
+ if (fsp_memory != NULL) {
+ printk(BIOS_DEBUG,
+ "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n",
+ fsp_memory);
+ data = fsp_memory->PhysicalStart;
+ printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
+ data = fsp_memory->ResourceLength;
+ printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
+ }
+
+ /* Verify all the HOBs are present */
+ if (fsp_verification_failure)
+ printk(BIOS_DEBUG,
+ "ERROR - Missing one or more required FSP HOBs!\n");
+
+ /* Display the HOBs */
+ print_hob_type_structure(0, hob_list_ptr);
+#endif
+
+ /* Get the address of the CBMEM region for the FSP reserved memory */
+ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
+ printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n",
+ fsp_reserved_memory_area);
+
+ /* Verify the order of CBMEM root and FSP memory */
+ if ((fsp_memory != NULL) && (cbmem_root != NULL) &&
+ (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG,
+ "ERROR - FSP reserved memory above CBMEM root!\n");
+ }
+
+ /* Verify that the FSP memory was properly reserved */
+ if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) ||
+ (fsp_memory->PhysicalStart !=
+ (unsigned int)fsp_reserved_memory_area))) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n");
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ if (cbmem_root != NULL) {
+ size_t delta_bytes = (unsigned int)smm_base
+ - cbmem_root->PhysicalStart
+ - cbmem_root->ResourceLength;
+ printk(BIOS_DEBUG,
+ "0x%08x: Chipset reserved bytes reported by FSP\n",
+ (unsigned int)delta_bytes);
+ die("Please verify the chipset reserved size\n");
+ }
+#endif
+ }
+
+ /* Verify the FSP 1.1 HOB interface */
+ if (fsp_verification_failure)
+ die("ERROR - Coreboot's requirements not met by FSP binary!\n");
+
+ /* Display the memory configuration */
+ report_memory_config();
+
+ /* Locate the memory configuration data to speed up the next reboot */
+ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr);
+ if (mrc_hob == NULL)
+ printk(BIOS_DEBUG,
+ "Memory Configuration Data Hob not present\n");
+ else {
+ pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob);
+ pei_ptr->data_to_save_size = ALIGN(
+ ((u32)GET_HOB_LENGTH(mrc_hob)), 16);
+ }
+}
+
+/* Initialize the UPD parameters for MemoryInit */
+__attribute__((weak)) void mainboard_memory_init_params(
+ struct romstage_params *params,
+ MEMORY_INIT_UPD *upd_ptr)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Display the UPD parameters for MemoryInit */
+__attribute__((weak)) void soc_display_memory_init_params(
+ const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
+{
+ printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
+ hexdump32(BIOS_SPEW, new, sizeof(*new));
+}
+
+/* Initialize the UPD parameters for MemoryInit */
+__attribute__((weak)) void soc_memory_init_params(
+ struct romstage_params *params,
+ MEMORY_INIT_UPD *upd)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
new file mode 100644
index 0000000..4561563
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/memmap.h>
+#include <fsp/ramstage.h>
+#include <fsp/util.h>
+#include <lib.h>
+#include <stage_cache.h>
+#include <string.h>
+#include <timestamp.h>
+
+/* SOC initialization after FSP silicon init */
+__attribute__((weak)) void soc_after_silicon_init(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Display SMM memory map */
+static void smm_memory_map(void)
+{
+ void *base;
+ size_t size;
+ int i;
+
+ printk(BIOS_SPEW, "SMM Memory Map\n");
+
+ smm_region(&base, &size);
+ printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size);
+
+ for (i = 0; i < SMM_SUBREGION_NUM; i++) {
+ if (smm_subregion(i, &base, &size))
+ continue;
+ printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size);
+ }
+}
+
+static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
+{
+ const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
+ int missing_hob = 0;
+ void *hob_list_ptr = get_hob_list();
+
+ if (!IS_ENABLED(CONFIG_DISPLAY_HOBS))
+ return;
+
+ /* Verify the HOBs */
+ if (hob_list_ptr == NULL) {
+ printk(BIOS_INFO, "ERROR - HOB pointer is NULL!\n");
+ return;
+ }
+
+ print_hob_type_structure(0, hob_list_ptr);
+
+ /*
+ * Verify that FSP is generating the required HOBs:
+ * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
+ * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
+ * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
+ * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
+ * 7.5: EFI_PEI_GRAPHICS_INFO_HOB verified below,
+ * if the ImageAttribute bit is set
+ * FSP_SMBIOS_MEMORY_INFO HOB verified by raminit
+ */
+ if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) &&
+ !get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) {
+ printk(BIOS_INFO, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
+ missing_hob = 1;
+ }
+
+ if (missing_hob)
+ printk(BIOS_INFO,
+ "ERROR - Missing one or more required FSP HOBs!\n");
+}
+
+static void fsp_run_silicon_init(int is_s3_wakeup)
+{
+ FSP_INFO_HEADER *fsp_info_header;
+ FSP_SILICON_INIT fsp_silicon_init;
+ SILICON_INIT_UPD *original_params;
+ SILICON_INIT_UPD silicon_init_params;
+ EFI_STATUS status;
+ UPD_DATA_REGION *upd_ptr;
+ VPD_DATA_REGION *vpd_ptr;
+
+ /* Find the FSP image */
+ fsp_info_header = fsp_get_fih();
+ if (fsp_info_header == NULL) {
+ printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
+ return;
+ }
+ print_fsp_info(fsp_info_header);
+
+ /* Initialize the UPD values */
+ vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
+ fsp_info_header->ImageBase);
+ printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr);
+ upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
+ fsp_info_header->ImageBase);
+ printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr);
+ original_params = (void *)((u8 *)upd_ptr +
+ upd_ptr->SiliconInitUpdOffset);
+ memcpy(&silicon_init_params, original_params,
+ sizeof(silicon_init_params));
+ soc_silicon_init_params(&silicon_init_params);
+
+ /* Locate VBT and pass to FSP GOP */
+ if (IS_ENABLED(CONFIG_GOP_SUPPORT))
+ load_vbt(is_s3_wakeup, &silicon_init_params);
+ mainboard_silicon_init_params(&silicon_init_params);
+
+ /* Display the UPD data */
+ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
+ soc_display_silicon_init_params(original_params,
+ &silicon_init_params);
+
+ /* Perform silicon initialization after RAM is configured */
+ printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
+ fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
+ + fsp_info_header->FspSiliconInitEntryOffset);
+ timestamp_add_now(TS_FSP_SILICON_INIT_START);
+ printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
+ &silicon_init_params, fsp_silicon_init);
+ status = fsp_silicon_init(&silicon_init_params);
+ timestamp_add_now(TS_FSP_SILICON_INIT_END);
+ printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
+
+ display_hob_info(fsp_info_header);
+ soc_after_silicon_init();
+}
+
+static void fsp_cache_save(struct prog *fsp)
+{
+ if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP))
+ smm_memory_map();
+
+ if (prog_entry(fsp) == NULL) {
+ printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n");
+ return;
+ }
+
+ stage_cache_add(STAGE_REFCODE, fsp);
+}
+
+static int fsp_find_and_relocate(struct prog *fsp)
+{
+ if (prog_locate(fsp)) {
+ printk(BIOS_ERR, "ERROR: Couldn't find %s\n", prog_name(fsp));
+ return -1;
+ }
+
+ if (fsp_relocate(fsp, prog_rdev(fsp))) {
+ printk(BIOS_ERR, "ERROR: FSP relocation failed.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+void intel_silicon_init(void)
+{
+ struct prog fsp = PROG_INIT(ASSET_REFCODE, "fsp.bin");
+ int is_s3_wakeup = acpi_is_wakeup_s3();
+
+ if (is_s3_wakeup) {
+ printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
+ stage_cache_load_stage(STAGE_REFCODE, &fsp);
+ } else {
+ fsp_find_and_relocate(&fsp);
+ printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
+ fsp_cache_save(&fsp);
+ }
+
+ /* FSP_INFO_HEADER is set as the program entry. */
+ fsp_update_fih(prog_entry(&fsp));
+
+ fsp_run_silicon_init(is_s3_wakeup);
+}
+
+/* Initialize the UPD parameters for SiliconInit */
+__attribute__((weak)) void mainboard_silicon_init_params(
+ SILICON_INIT_UPD *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+};
+
+/* Display the UPD parameters for SiliconInit */
+__attribute__((weak)) void soc_display_silicon_init_params(
+ const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
+{
+ printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
+ hexdump32(BIOS_SPEW, new, sizeof(*new));
+}
+
+/* Initialize the UPD parameters for SiliconInit */
+__attribute__((weak)) void soc_silicon_init_params(SILICON_INIT_UPD *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
new file mode 100644
index 0000000..541f128
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -0,0 +1,413 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/cbfs.h>
+#include <arch/stages.h>
+#include <arch/early_variables.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <cpu/x86/mtrr.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <elog.h>
+#include <fsp/util.h>
+#include <memory_info.h>
+#include <reset.h>
+#include <romstage_handoff.h>
+#include <smbios.h>
+#include <soc/intel/common/mrc_cache.h>
+#include <soc/intel/common/util.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include <soc/spi.h>
+#include <stage_cache.h>
+#include <timestamp.h>
+#include <tpm.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
+{
+ void *top_of_stack;
+ struct pei_data pei_data;
+ struct romstage_params params = {
+ .pei_data = &pei_data,
+ .chipset_context = fih,
+ };
+
+ post_code(0x30);
+
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ memset(&pei_data, 0, sizeof(pei_data));
+
+ /* Display parameters */
+ printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
+ CONFIG_MMCONF_BASE_ADDRESS);
+ printk(BIOS_INFO, "Using FSP 1.1");
+
+ /* Display FSP banner */
+ print_fsp_info(fih);
+
+ /* Get power state */
+ params.power_state = fill_power_state();
+
+ /*
+ * Read and print board version. Done after SOC romstage
+ * in case PCH needs to be configured to talk to the EC.
+ */
+ if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
+ printk(BIOS_INFO, "MLB: board version %d\n", board_id());
+
+ /* Call into mainboard. */
+ mainboard_romstage_entry(¶ms);
+ soc_after_ram_init(¶ms);
+ post_code(0x38);
+
+ top_of_stack = setup_stack_and_mtrrs();
+
+ printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
+ timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START);
+ return top_of_stack;
+}
+
+void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
+{
+ return romstage_main(fih);
+}
+
+/* Entry from the mainboard. */
+void romstage_common(struct romstage_params *params)
+{
+ const struct mrc_saved_data *cache;
+ struct romstage_handoff *handoff;
+ struct pei_data *pei_data;
+
+ post_code(0x32);
+
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
+ pei_data = params->pei_data;
+ pei_data->boot_mode = params->power_state->prev_sleep_state;
+
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+ if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
+ boot_count_increment();
+#endif
+
+ /* Perform remaining SOC initialization */
+ soc_pre_ram_init(params);
+ post_code(0x33);
+
+ /* Check recovery and MRC cache */
+ params->pei_data->saved_data_size = 0;
+ params->pei_data->saved_data = NULL;
+ if (!params->pei_data->disable_saved_data) {
+ if (recovery_mode_enabled()) {
+ /* Recovery mode does not use MRC cache */
+ printk(BIOS_DEBUG,
+ "Recovery mode: not using MRC cache.\n");
+ } else if (!mrc_cache_get_current(&cache)) {
+ /* MRC cache found */
+ params->pei_data->saved_data_size = cache->size;
+ params->pei_data->saved_data = &cache->data[0];
+ } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) {
+ /* Waking from S3 and no cache. */
+ printk(BIOS_DEBUG,
+ "No MRC cache found in S3 resume path.\n");
+ post_code(POST_RESUME_FAILURE);
+ hard_reset();
+ } else {
+ printk(BIOS_DEBUG, "No MRC cache found.\n");
+ mainboard_check_ec_image(params);
+ }
+ }
+
+ /* Initialize RAM */
+ raminit(params);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
+ /* Save MRC output */
+ printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
+ pei_data->data_to_save_size);
+ if (params->pei_data->boot_mode != SLEEP_STATE_S3) {
+ if (params->pei_data->data_to_save_size != 0 &&
+ params->pei_data->data_to_save != NULL) {
+ mrc_cache_stash_data(params->pei_data->data_to_save,
+ params->pei_data->data_to_save_size);
+ }
+ }
+
+ /* Save DIMM information */
+ mainboard_save_dimm_info(params);
+
+ /* Create romstage handof information */
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = (params->power_state->prev_sleep_state ==
+ SLEEP_STATE_S3);
+ else {
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
+ hard_reset();
+ }
+
+ if (IS_ENABLED(CONFIG_LPC_TPM))
+ init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3);
+}
+
+void after_cache_as_ram_stage(void)
+{
+ /* Load the ramstage. */
+ copy_and_run();
+ die("ERROR - Failed to load ramstage!");
+}
+
+/* Initialize the power state */
+__attribute__((weak)) struct chipset_power_state *fill_power_state(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return NULL;
+}
+
+__attribute__((weak)) void mainboard_check_ec_image(
+ struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+ struct pei_data *pei_data;
+
+ pei_data = params->pei_data;
+ if (params->pei_data->boot_mode == SLEEP_STATE_S0) {
+ /* Ensure EC is running RO firmware. */
+ google_chromeec_check_ec_image(EC_IMAGE_RO);
+ }
+#endif
+}
+
+/* Board initialization before and after RAM is enabled */
+__attribute__((weak)) void mainboard_romstage_entry(
+ struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+
+ post_code(0x31);
+
+ /* Initliaze memory */
+ romstage_common(params);
+}
+
+/* Save the DIMM information for SMBIOS table 17 */
+__attribute__((weak)) void mainboard_save_dimm_info(
+ struct romstage_params *params)
+{
+ int channel;
+ CHANNEL_INFO *channel_info;
+ int dimm;
+ DIMM_INFO *dimm_info;
+ int dimm_max;
+ void *hob_list_ptr;
+ EFI_HOB_GUID_TYPE *hob_ptr;
+ int index;
+ struct memory_info *mem_info;
+ FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
+ const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
+
+ /* Locate the memory info HOB, presence validated by raminit */
+ hob_list_ptr = fsp_get_hob_list();
+ hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr);
+ memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1);
+
+ /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
+ if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) {
+ printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n");
+ printk(BIOS_DEBUG, " 0x%02x: Revision\n",
+ memory_info_hob->Revision);
+ printk(BIOS_DEBUG, " 0x%02x: MemoryType\n",
+ memory_info_hob->MemoryType);
+ printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n",
+ memory_info_hob->MemoryFrequencyInMHz);
+ printk(BIOS_DEBUG, " %d: DataWidth in bits\n",
+ memory_info_hob->DataWidth);
+ printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n",
+ memory_info_hob->ErrorCorrectionType);
+ printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n",
+ memory_info_hob->ChannelCount);
+ for (channel = 0; channel < memory_info_hob->ChannelCount;
+ channel++) {
+ channel_info = &memory_info_hob->ChannelInfo[channel];
+ printk(BIOS_DEBUG, " Channel %d\n", channel);
+ printk(BIOS_DEBUG, " 0x%02x: ChannelId\n",
+ channel_info->ChannelId);
+ printk(BIOS_DEBUG, " 0x%02x: DimmCount\n",
+ channel_info->DimmCount);
+ for (dimm = 0; dimm < channel_info->DimmCount;
+ dimm++) {
+ dimm_info = &channel_info->DimmInfo[dimm];
+ printk(BIOS_DEBUG, " DIMM %d\n", dimm);
+ printk(BIOS_DEBUG, " 0x%02x: DimmId\n",
+ dimm_info->DimmId);
+ printk(BIOS_DEBUG, " %d: SizeInMb\n",
+ dimm_info->SizeInMb);
+ }
+ }
+ }
+
+ /*
+ * Allocate CBMEM area for DIMM information used to populate SMBIOS
+ * table 17
+ */
+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+ printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
+ if (mem_info == NULL)
+ return;
+ memset(mem_info, 0, sizeof(*mem_info));
+
+ /* Describe the first N DIMMs in the system */
+ index = 0;
+ dimm_max = ARRAY_SIZE(mem_info->dimm);
+ for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
+ if (index >= dimm_max)
+ break;
+ channel_info = &memory_info_hob->ChannelInfo[channel];
+ for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
+ if (index >= dimm_max)
+ break;
+ dimm_info = &channel_info->DimmInfo[dimm];
+
+ /* Populate the DIMM information */
+ if (dimm_info->SizeInMb) {
+ mem_info->dimm[index].dimm_size =
+ dimm_info->SizeInMb;
+ mem_info->dimm[index].ddr_type =
+ memory_info_hob->MemoryType;
+ mem_info->dimm[index].ddr_frequency =
+ memory_info_hob->MemoryFrequencyInMHz;
+ mem_info->dimm[index].channel_num =
+ channel_info->ChannelId;
+ mem_info->dimm[index].dimm_num =
+ dimm_info->DimmId;
+ switch (memory_info_hob->DataWidth) {
+ default:
+ case 8:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_8;
+ break;
+
+ case 16:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_16;
+ break;
+
+ case 32:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_32;
+ break;
+
+ case 64:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_64;
+ break;
+
+ case 128:
+ mem_info->dimm[index].bus_width =
+ MEMORY_BUS_WIDTH_128;
+ break;
+ }
+
+ /* Add any mainboard specific information */
+ mainboard_add_dimm_info(params, mem_info,
+ channel, dimm, index);
+ index++;
+ }
+ }
+ }
+ mem_info->dimm_cnt = index;
+ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
+
+/* Add any mainboard specific information */
+__attribute__((weak)) void mainboard_add_dimm_info(
+ struct romstage_params *params,
+ struct memory_info *mem_info,
+ int channel, int dimm, int index)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Get the memory configuration data */
+__attribute__((weak)) int mrc_cache_get_current(
+ const struct mrc_saved_data **cache)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return -1;
+}
+
+/* Save the memory configuration data */
+__attribute__((weak)) int mrc_cache_stash_data(void *data, size_t size)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return -1;
+}
+
+/* Transition RAM from off or self-refresh to active */
+__attribute__((weak)) void raminit(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ post_code(0x34);
+ die("ERROR - No RAM initialization specified!\n");
+}
+
+void ramstage_cache_invalid(void)
+{
+ if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE))
+ /* Perform cold reset on invalid ramstage cache. */
+ hard_reset();
+}
+
+/* Display the memory configuration */
+__attribute__((weak)) void report_memory_config(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Choose top of stack and setup MTRRs */
+__attribute__((weak)) void *setup_stack_and_mtrrs(void)
+{
+ printk(BIOS_ERR, "WEAK: %s/%s called\n", __FILE__, __func__);
+ die("ERROR - Must specify top of stack!\n");
+ return NULL;
+}
+
+/* SOC initialization after RAM is enabled */
+__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* SOC initialization before RAM is enabled */
+__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
new file mode 100644
index 0000000..8f3c78e
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <fsp/memmap.h>
+#include <fsp/romstage.h>
+#include <fsp/stack.h>
+#include <soc/intel/common/util.h>
+#include <stdlib.h>
+
+const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
+
+/*
+ * Romstage needs quite a bit of stack for decompressing images since the lzma
+ * lib keeps its state on the stack during romstage.
+ */
+static unsigned long choose_top_of_stack(void)
+{
+ unsigned long stack_top;
+
+ /* cbmem_add() does a find() before add(). */
+ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
+ romstage_ram_stack_size);
+ stack_top += romstage_ram_stack_size;
+ return stack_top;
+}
+
+/*
+ * setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use.
+ */
+void *setup_stack_and_mtrrs(void)
+{
+ size_t alignment;
+ uint32_t aligned_ram;
+ uint32_t mtrr_mask_upper;
+ uint32_t max_mtrrs;
+ uint32_t num_mtrrs;
+ uint32_t *slot;
+ unsigned long top_of_stack;
+
+ /* Display the MTTRs */
+ soc_display_mtrrs();
+
+ /* Top of stack needs to be aligned to a 8-byte boundary. */
+ top_of_stack = choose_top_of_stack();
+ slot = (void *)top_of_stack;
+ num_mtrrs = 0;
+ max_mtrrs = soc_get_variable_mtrr_count(NULL);
+
+ /*
+ * The upper bits of the MTRR mask need to set according to the number
+ * of physical address bits.
+ */
+ mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
+ alignment = mmap_region_granluarity();
+ aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size,
+ alignment);
+
+ /*
+ * The order for each MTRR is value then base with upper 32-bits of
+ * each value coming before the lower 32-bits. The reasoning for
+ * this ordering is to create a stack layout like the following:
+ *
+ * +36: MTRR mask 1 63:32
+ * +32: MTRR mask 1 31:0
+ * +28: MTRR base 1 63:32
+ * +24: MTRR base 1 31:0
+ * +20: MTRR mask 0 63:32
+ * +16: MTRR mask 0 31:0
+ * +12: MTRR base 0 63:32
+ * +8: MTRR base 0 31:0
+ * +4: Number of MTRRs to setup (described above)
+ * +0: Number of variable MTRRs to clear
+ */
+
+ /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /*
+ * +-------------------------+ Top of RAM (aligned)
+ * | System Management Mode |
+ * | code and data | Length: CONFIG_TSEG_SIZE
+ * | (TSEG) |
+ * +-------------------------+ SMM base (aligned)
+ * | |
+ * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
+ * | |
+ * +-------------------------+ top_of_ram (aligned)
+ * | |
+ * | CBMEM Root |
+ * | |
+ * +-------------------------+
+ * | |
+ * | FSP Reserved Memory |
+ * | |
+ * +-------------------------+
+ * | |
+ * | Various CBMEM Entries |
+ * | |
+ * +-------------------------+ top_of_stack (8 byte aligned)
+ * | |
+ * | stack (CBMEM Entry) |
+ * | |
+ * +-------------------------+
+ */
+
+ /*
+ * Cache the stack and the other CBMEM entries as well as part or all
+ * of the FSP reserved memory region.
+ */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ void *smm_base;
+ size_t smm_size;
+ uint32_t tseg_base;
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is not
+ * restricted to SMM mode until SMM has been relocated. By setting
+ * the region to cacheable it provides faster access when relocating
+ * the SMM handler as well as using the TSEG region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ tseg_base = (uint32_t)smm_base;
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+#endif
+
+ /* Cache the ROM as WP just below 4GiB. */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+ num_mtrrs++;
+
+ /* Validate the MTRR usage */
+ if (num_mtrrs > max_mtrrs) {
+ printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d",
+ max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs);
+ die("ERROR - MTRR use count incorrect!\n");
+ }
+
+ /*
+ * Save the number of MTRRs to setup and clear. Return the stack
+ * location pointing to the number of MTRRs.
+ */
+ slot = stack_push32(slot, num_mtrrs);
+ slot = stack_push32(slot, max_mtrrs);
+ return slot;
+}
+
diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c
new file mode 100644
index 0000000..5ad24c0
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/stage_cache.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <fsp/memmap.h>
+#include <stage_cache.h>
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+ printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
+ *base = NULL;
+ *size = 0;
+ }
+}
diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c
new file mode 100644
index 0000000..0595050
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/vbt.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/ramstage.h>
+#include <fsp/util.h>
+#include <lib.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Locate VBT and pass it to FSP GOP */
+void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
+{
+ const optionrom_vbt_t *vbt_data;
+ uint32_t vbt_len;
+
+ /* Check boot mode - for S3 resume path VBT loading is not needed */
+ if (s3_resume) {
+ vbt_data = NULL;
+ printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n");
+ } else {
+ if (developer_mode_enabled() || recovery_mode_enabled()) {
+ /* Get VBT data */
+ vbt_data = fsp_get_vbt(&vbt_len);
+ if (vbt_data != NULL)
+ printk(BIOS_DEBUG, "Passing VBT to GOP\n");
+ else
+ printk(BIOS_DEBUG, "VBT not found!\n");
+ } else
+ vbt_data = NULL;
+ }
+ params->GraphicsConfigPtr = (u32)vbt_data;
+}
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 5a41056..e6f2275 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -17,6 +17,10 @@ config CPU_SPECIFIC_OPTIONS
select COLLECT_TIMESTAMPS
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+ select FSP_RAM_INIT
+ select FSP_ROMSTAGE
+ select FSP_STACK
+ select FSP_STAGE_CACHE
select HAS_PRECBMEM_TIMESTAMP_REGION
select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
@@ -33,11 +37,7 @@ config CPU_SPECIFIC_OPTIONS
select REG_SCRIPT
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
- select SOC_INTEL_COMMON_FSP_RAM_INIT
- select SOC_INTEL_COMMON_FSP_ROMSTAGE
select SOC_INTEL_COMMON_RESET
- select SOC_INTEL_COMMON_STACK
- select SOC_INTEL_COMMON_STAGE_CACHE
select SMM_TSEG
select SMP
select SPI_FLASH
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 41a43ee..8d1ae81 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -28,7 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
-#include <soc/intel/common/memmap.h>
+#include <fsp/memmap.h>
#include <reg_script.h>
#include <soc/iosf.h>
#include <soc/msr.h>
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index d54ff66..70a5c71 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -25,7 +25,7 @@
#include <soc/nvs.h>
#if CONFIG_GOP_SUPPORT
-#include <soc/intel/common/gma.h>
+#include <fsp/gma.h>
int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif
diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h
index f171243..9b40db6 100644
--- a/src/soc/intel/braswell/include/soc/ramstage.h
+++ b/src/soc/intel/braswell/include/soc/ramstage.h
@@ -23,7 +23,7 @@
#include <chip.h>
#include <device/device.h>
-#include <soc/intel/common/ramstage.h>
+#include <fsp/ramstage.h>
/*
* The soc_init_pre_device() function is called prior to device
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 0f24f71..6dfe8a8 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -23,10 +23,10 @@
#include <stdint.h>
#include <arch/cpu.h>
+#include <fsp/romstage.h>
#include <fsp/util.h>
#include <soc/pei_data.h>
#include <soc/pm.h>
-#include <soc/intel/common/romstage.h>
void gfx_init(void);
void tco_disable(void);
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index 52bba3e..24e8b3b 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -21,7 +21,7 @@
#include <arch/io.h>
#include <cbmem.h>
#include <console/console.h>
-#include <soc/intel/common/memmap.h>
+#include <fsp/memmap.h>
#include <soc/iosf.h>
#include <soc/smm.h>
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 390e050..67af087 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -25,8 +25,8 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <fsp/memmap.h>
#include <fsp/util.h>
-#include <soc/intel/common/memmap.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 2454c6b..c6e8936 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -40,7 +40,6 @@
#include <soc/pm.h>
#include <soc/ramstage.h>
#include <soc/intel/common/acpi.h>
-#include <soc/intel/common/ramstage.h>
#include <boardid.h>
#include <stdlib.h>
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 43c52b5..17c2809 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -40,35 +40,10 @@ config DISPLAY_SMM_MEMORY_MAP
bool "SMM: Display the SMM memory map"
default n
-config SOC_INTEL_COMMON_FSP_RAM_INIT
- bool "FSP: Use the common raminit.c module"
- default n
- depends on PLATFORM_USES_FSP1_1
-
-config SOC_INTEL_COMMON_FSP_ROMSTAGE
- bool
- default n
- depends on PLATFORM_USES_FSP1_1
-
config SOC_INTEL_COMMON_RESET
bool
default n
-config SOC_INTEL_COMMON_STACK
- bool
- default n
- depends on PLATFORM_USES_FSP1_1
-
-config SOC_INTEL_COMMON_STAGE_CACHE
- bool
- default n
- depends on PLATFORM_USES_FSP1_1
-
-config ROMSTAGE_RAM_STACK_SIZE
- hex "Size of the romstage RAM stack in bytes"
- default 0x5000
- depends on SOC_INTEL_COMMON_STACK
-
config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
bool
default n
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 8827ada..53d3b71 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -3,21 +3,14 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c
romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE) += romstage.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c
-romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c
+romstage-y += util.c
-ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c
ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c
-ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c
-ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
+ramstage-y += util.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
# Create and add the MRC cache to the cbfs image
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
deleted file mode 100644
index a1b677a..0000000
--- a/src/soc/intel/common/fsp_ramstage.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/acpi.h>
-#include <cbmem.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <fsp/util.h>
-#include <lib.h>
-#include <soc/intel/common/memmap.h>
-#include <soc/intel/common/ramstage.h>
-#include <stage_cache.h>
-#include <string.h>
-#include <timestamp.h>
-
-/* SOC initialization after FSP silicon init */
-__attribute__((weak)) void soc_after_silicon_init(void)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Display SMM memory map */
-static void smm_memory_map(void)
-{
- void *base;
- size_t size;
- int i;
-
- printk(BIOS_SPEW, "SMM Memory Map\n");
-
- smm_region(&base, &size);
- printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size);
-
- for (i = 0; i < SMM_SUBREGION_NUM; i++) {
- if (smm_subregion(i, &base, &size))
- continue;
- printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size);
- }
-}
-
-static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
-{
- const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
- int missing_hob = 0;
- void *hob_list_ptr = get_hob_list();
-
- if (!IS_ENABLED(CONFIG_DISPLAY_HOBS))
- return;
-
- /* Verify the HOBs */
- if (hob_list_ptr == NULL) {
- printk(BIOS_INFO, "ERROR - HOB pointer is NULL!\n");
- return;
- }
-
- print_hob_type_structure(0, hob_list_ptr);
-
- /*
- * Verify that FSP is generating the required HOBs:
- * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
- * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
- * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
- * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
- * 7.5: EFI_PEI_GRAPHICS_INFO_HOB verified below,
- * if the ImageAttribute bit is set
- * FSP_SMBIOS_MEMORY_INFO HOB verified by raminit
- */
- if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) &&
- !get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) {
- printk(BIOS_INFO, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
- missing_hob = 1;
- }
-
- if (missing_hob)
- printk(BIOS_INFO,
- "ERROR - Missing one or more required FSP HOBs!\n");
-}
-
-static void fsp_run_silicon_init(int is_s3_wakeup)
-{
- FSP_INFO_HEADER *fsp_info_header;
- FSP_SILICON_INIT fsp_silicon_init;
- SILICON_INIT_UPD *original_params;
- SILICON_INIT_UPD silicon_init_params;
- EFI_STATUS status;
- UPD_DATA_REGION *upd_ptr;
- VPD_DATA_REGION *vpd_ptr;
-
- /* Find the FSP image */
- fsp_info_header = fsp_get_fih();
- if (fsp_info_header == NULL) {
- printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
- return;
- }
- print_fsp_info(fsp_info_header);
-
- /* Initialize the UPD values */
- vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
- fsp_info_header->ImageBase);
- printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr);
- upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
- fsp_info_header->ImageBase);
- printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr);
- original_params = (void *)((u8 *)upd_ptr +
- upd_ptr->SiliconInitUpdOffset);
- memcpy(&silicon_init_params, original_params,
- sizeof(silicon_init_params));
- soc_silicon_init_params(&silicon_init_params);
-
- /* Locate VBT and pass to FSP GOP */
- if (IS_ENABLED(CONFIG_GOP_SUPPORT))
- load_vbt(is_s3_wakeup, &silicon_init_params);
- mainboard_silicon_init_params(&silicon_init_params);
-
- /* Display the UPD data */
- if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
- soc_display_silicon_init_params(original_params,
- &silicon_init_params);
-
- /* Perform silicon initialization after RAM is configured */
- printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
- fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
- + fsp_info_header->FspSiliconInitEntryOffset);
- timestamp_add_now(TS_FSP_SILICON_INIT_START);
- printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
- &silicon_init_params, fsp_silicon_init);
- status = fsp_silicon_init(&silicon_init_params);
- timestamp_add_now(TS_FSP_SILICON_INIT_END);
- printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
-
- display_hob_info(fsp_info_header);
- soc_after_silicon_init();
-}
-
-static void fsp_cache_save(struct prog *fsp)
-{
- if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP))
- smm_memory_map();
-
- if (prog_entry(fsp) == NULL) {
- printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n");
- return;
- }
-
- stage_cache_add(STAGE_REFCODE, fsp);
-}
-
-static int fsp_find_and_relocate(struct prog *fsp)
-{
- if (prog_locate(fsp)) {
- printk(BIOS_ERR, "ERROR: Couldn't find %s\n", prog_name(fsp));
- return -1;
- }
-
- if (fsp_relocate(fsp, prog_rdev(fsp))) {
- printk(BIOS_ERR, "ERROR: FSP relocation failed.\n");
- return -1;
- }
-
- return 0;
-}
-
-void intel_silicon_init(void)
-{
- struct prog fsp = PROG_INIT(ASSET_REFCODE, "fsp.bin");
- int is_s3_wakeup = acpi_is_wakeup_s3();
-
- if (is_s3_wakeup) {
- printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
- stage_cache_load_stage(STAGE_REFCODE, &fsp);
- } else {
- fsp_find_and_relocate(&fsp);
- printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
- fsp_cache_save(&fsp);
- }
-
- /* FSP_INFO_HEADER is set as the program entry. */
- fsp_update_fih(prog_entry(&fsp));
-
- fsp_run_silicon_init(is_s3_wakeup);
-}
-
-/* Initialize the UPD parameters for SiliconInit */
-__attribute__((weak)) void mainboard_silicon_init_params(
- SILICON_INIT_UPD *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-};
-
-/* Display the UPD parameters for SiliconInit */
-__attribute__((weak)) void soc_display_silicon_init_params(
- const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
-{
- printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
- hexdump32(BIOS_SPEW, new, sizeof(*new));
-}
-
-/* Initialize the UPD parameters for SiliconInit */
-__attribute__((weak)) void soc_silicon_init_params(SILICON_INIT_UPD *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h
deleted file mode 100644
index 64b2a28..0000000
--- a/src/soc/intel/common/gma.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Chromium OS Authors
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _GMA_H_
-#define _GMA_H_
-
-#include <types.h>
-
-/* IGD PCI Configuration register */
-#define ASLS 0xfc /* OpRegion Base */
-#define SWSCI 0xe8 /* SWSCI Register */
-#define GSSCIE (1 << 0) /* SCI Event trigger */
-#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */
-
-/* mailbox 0: header */
-typedef struct {
- u8 signature[16];
- u32 size;
- u32 version;
- u8 sbios_version[32];
- u8 vbios_version[16];
- u8 driver_version[16];
- u32 mailboxes;
- u8 reserved[164];
-} __attribute__((packed)) opregion_header_t;
-
-#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
-#define IGD_OPREGION_VERSION 2
-
-#define IGD_MBOX1 (1 << 0)
-#define IGD_MBOX2 (1 << 1)
-#define IGD_MBOX3 (1 << 2)
-#define IGD_MBOX4 (1 << 3)
-#define IGD_MBOX5 (1 << 4)
-
-#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
- IGD_MBOX4 | IGD_MBOX5)
-#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
-
-#define SBIOS_VERSION_SIZE 32
-
-/* mailbox 1: public acpi methods */
-typedef struct {
- u32 drdy;
- u32 csts;
- u32 cevt;
- u8 reserved1[20];
- u32 didl[8];
- u32 cpdl[8];
- u32 cadl[8];
- u32 nadl[8];
- u32 aslp;
- u32 tidx;
- u32 chpd;
- u32 clid;
- u32 cdck;
- u32 sxsw;
- u32 evts;
- u32 cnot;
- u32 nrdy;
- u8 reserved2[60];
-} __attribute__((packed)) opregion_mailbox1_t;
-
-/* mailbox 2: software sci interface */
-typedef struct {
- u32 scic;
- u32 parm;
- u32 dslp;
- u8 reserved[244];
-} __attribute__((packed)) opregion_mailbox2_t;
-
-/* mailbox 3: power conservation */
-typedef struct {
- u32 ardy;
- u32 aslc;
- u32 tche;
- u32 alsi;
- u32 bclp;
- u32 pfit;
- u32 cblv;
- u16 bclm[20];
- u32 cpfm;
- u32 epfm;
- u8 plut[74];
- u32 pfmb;
- u32 ccdv;
- u32 pcft;
- u8 reserved[94];
-} __attribute__((packed)) opregion_mailbox3_t;
-
-#define IGD_BACKLIGHT_BRIGHTNESS 0xff
-#define IGD_INITIAL_BRIGHTNESS 0x64
-
-#define IGD_FIELD_VALID (1 << 31)
-#define IGD_WORD_FIELD_VALID (1 << 15)
-#define IGD_PFIT_STRETCH 6
-
-/* mailbox 4: vbt */
-typedef struct {
- u8 gvd1[7168];
-} __attribute__((packed)) opregion_vbt_t;
-
-/* IGD OpRegion */
-typedef struct {
- opregion_header_t header;
- opregion_mailbox1_t mailbox1;
- opregion_mailbox2_t mailbox2;
- opregion_mailbox3_t mailbox3;
- opregion_vbt_t vbt;
-} __attribute__((packed)) igd_opregion_t;
-
-/* Intel Video BIOS (Option ROM) */
-typedef struct {
- u16 signature;
- u8 size;
- u8 reserved[21];
- u16 pcir_offset;
- u16 vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
-
-#define OPROM_SIGNATURE 0xaa55
-
-typedef struct {
- u32 signature;
- u16 vendor;
- u16 device;
- u16 reserved1;
- u16 length;
- u8 revision;
- u8 classcode[3];
- u16 imagelength;
- u16 coderevision;
- u8 codetype;
- u8 indicator;
- u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
-
-typedef struct {
- u8 hdr_signature[20];
- u16 hdr_version;
- u16 hdr_size;
- u16 hdr_vbt_size;
- u8 hdr_vbt_checksum;
- u8 hdr_reserved;
- u32 hdr_vbt_datablock;
- u32 hdr_aim[4];
- u8 datahdr_signature[16];
- u16 datahdr_version;
- u16 datahdr_size;
- u16 datahdr_datablocksize;
- u8 coreblock_id;
- u16 coreblock_size;
- u16 coreblock_biossize;
- u8 coreblock_biostype;
- u8 coreblock_releasestatus;
- u8 coreblock_hwsupported;
- u8 coreblock_integratedhw;
- u8 coreblock_biosbuild[4];
- u8 coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
-
-#define VBT_SIGNATURE 0x54425624
-
-#endif /* _GMA_H_ */
-
diff --git a/src/soc/intel/common/memmap.h b/src/soc/intel/common/memmap.h
deleted file mode 100644
index 3d51539..0000000
--- a/src/soc/intel/common/memmap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _COMMON_MEMMAP_H_
-#define _COMMON_MEMMAP_H_
-
-#include <types.h>
-
-/*
- * mmap_region_granluarity must to return a size which is a positive non-zero
- * integer multiple of the SMM size when SMM is in use. When not using SMM,
- * this value should be set to 8 MiB.
- */
-size_t mmap_region_granluarity(void);
-
-/* Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
-
-enum {
- /* SMM handler area. */
- SMM_SUBREGION_HANDLER,
- /* SMM cache region. */
- SMM_SUBREGION_CACHE,
- /* Chipset specific area. */
- SMM_SUBREGION_CHIPSET,
- /* Total sub regions supported. */
- SMM_SUBREGION_NUM,
-};
-
-/* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
-
-#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
deleted file mode 100644
index 0779c55..0000000
--- a/src/soc/intel/common/raminit.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014-2015 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <cbmem.h>
-#include <console/console.h>
-#include <fsp/util.h>
-#include <lib.h> /* hexdump */
-#include <reset.h>
-#include <soc/intel/common/memmap.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <string.h>
-#include <timestamp.h>
-
-void raminit(struct romstage_params *params)
-{
- const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
- EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
- FSP_INFO_HEADER *fsp_header;
- EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory;
- FSP_MEMORY_INIT fsp_memory_init;
- FSP_MEMORY_INIT_PARAMS fsp_memory_init_params;
- const EFI_GUID fsp_reserved_guid =
- FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
- void *fsp_reserved_memory_area;
- FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer;
- void *hob_list_ptr;
- FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
- const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
- MEMORY_INIT_UPD memory_init_params;
- const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
- u32 *mrc_hob;
- u32 fsp_reserved_bytes;
- MEMORY_INIT_UPD *original_params;
- struct pei_data *pei_ptr;
- EFI_STATUS status;
- VPD_DATA_REGION *vpd_ptr;
- UPD_DATA_REGION *upd_ptr;
- int fsp_verification_failure = 0;
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
- unsigned long int data;
- EFI_PEI_HOB_POINTERS hob_ptr;
-#endif
-
- /*
- * Find and copy the UPD region to the stack so the platform can modify
- * the settings if needed. Modifications to the UPD buffer are done in
- * the platform callback code. The platform callback code is also
- * responsible for assigning the UpdDataRngPtr to this buffer if any
- * updates are made. The default state is to leave the UpdDataRngPtr
- * set to NULL. This indicates that the FSP code will use the UPD
- * region in the FSP binary.
- */
- post_code(0x34);
- fsp_header = params->chipset_context;
- vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
- fsp_header->ImageBase);
- printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
- upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
- fsp_header->ImageBase);
- printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr);
- original_params = (void *)((u8 *)upd_ptr +
- upd_ptr->MemoryInitUpdOffset);
- memcpy(&memory_init_params, original_params,
- sizeof(memory_init_params));
-
- /* Zero fill RT Buffer data and start populating fields. */
- memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
- pei_ptr = params->pei_data;
- if (pei_ptr->boot_mode == SLEEP_STATE_S3) {
- fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
- } else if (pei_ptr->saved_data != NULL) {
- fsp_rt_common_buffer.BootMode =
- BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
- } else {
- fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION;
- }
- fsp_rt_common_buffer.UpdDataRgnPtr = &memory_init_params;
- fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size();
-
- /* Get any board specific changes */
- fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data;
- fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer;
- fsp_memory_init_params.HobListPtr = &hob_list_ptr;
-
- /* Update the UPD data */
- soc_memory_init_params(params, &memory_init_params);
- mainboard_memory_init_params(params, &memory_init_params);
- post_code(0x36);
-
- /* Display the UPD data */
- if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
- soc_display_memory_init_params(original_params,
- &memory_init_params);
-
- /* Call FspMemoryInit to initialize RAM */
- fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase
- + fsp_header->FspMemoryInitEntryOffset);
- printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init);
- printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n",
- fsp_memory_init_params.NvsBufferPtr);
- printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n",
- fsp_memory_init_params.RtBufferPtr);
- printk(BIOS_SPEW, " 0x%p: HobListPtr\n",
- fsp_memory_init_params.HobListPtr);
-
- timestamp_add_now(TS_FSP_MEMORY_INIT_START);
- status = fsp_memory_init(&fsp_memory_init_params);
- post_code(0x37);
- timestamp_add_now(TS_FSP_MEMORY_INIT_END);
-
- printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
- if (status != EFI_SUCCESS)
- die("ERROR - FspMemoryInit failed to initialize memory!\n");
-
- /* Locate the FSP reserved memory area */
- fsp_reserved_bytes = 0;
- fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr);
- if (fsp_memory == NULL) {
- fsp_verification_failure = 1;
- printk(BIOS_DEBUG,
- "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n");
- } else {
- fsp_reserved_bytes = fsp_memory->ResourceLength;
- printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n",
- (unsigned long int)fsp_reserved_bytes);
- }
-
- /* Display SMM area */
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
- char *smm_base;
- size_t smm_size;
-
- smm_region((void **)&smm_base, &smm_size);
- printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size);
- printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base);
-#endif
-
- /* Migrate CAR data */
- printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
- if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
- cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
- fsp_reserved_bytes);
- } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
- fsp_reserved_bytes)) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
- printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
- /* Failed S3 resume, reset to come up cleanly */
- hard_reset();
-#endif
- }
-
- /* Save the FSP runtime parameters. */
- fsp_set_runtime(fsp_header, hob_list_ptr);
-
- /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */
- cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr);
- if (cbmem_root == NULL) {
- fsp_verification_failure = 1;
- printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n");
- printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n",
- fsp_rt_common_buffer.BootLoaderTolumSize);
- }
-
- /* Locate the FSP_SMBIOS_MEMORY_INFO HOB */
- memory_info_hob = get_next_guid_hob(&memory_info_hob_guid,
- hob_list_ptr);
- if (NULL == memory_info_hob) {
- printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n");
- fsp_verification_failure = 1;
- } else {
- printk(BIOS_DEBUG,
- "FSP_SMBIOS_MEMORY_INFO HOB: 0x%p\n",
- memory_info_hob);
- }
-
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
- if (hob_list_ptr == NULL)
- die("ERROR - HOB pointer is NULL!\n");
-
- /*
- * Verify that FSP is generating the required HOBs:
- * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
- * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified above
- * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified below
- * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified above
- * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit
- * FSP_SMBIOS_MEMORY_INFO HOB verified above
- */
- if (NULL != cbmem_root) {
- printk(BIOS_DEBUG,
- "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n",
- cbmem_root);
- data = cbmem_root->PhysicalStart;
- printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
- data = cbmem_root->ResourceLength;
- printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
- }
- hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
- if (NULL == hob_ptr.Raw) {
- printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
- fsp_verification_failure =
- (params->pei_data->saved_data == NULL) ? 1 : 0;
- } else {
- printk(BIOS_DEBUG,
- "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n",
- hob_ptr.Raw);
- }
- if (fsp_memory != NULL) {
- printk(BIOS_DEBUG,
- "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n",
- fsp_memory);
- data = fsp_memory->PhysicalStart;
- printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
- data = fsp_memory->ResourceLength;
- printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
- }
-
- /* Verify all the HOBs are present */
- if (fsp_verification_failure)
- printk(BIOS_DEBUG,
- "ERROR - Missing one or more required FSP HOBs!\n");
-
- /* Display the HOBs */
- print_hob_type_structure(0, hob_list_ptr);
-#endif
-
- /* Get the address of the CBMEM region for the FSP reserved memory */
- fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
- printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n",
- fsp_reserved_memory_area);
-
- /* Verify the order of CBMEM root and FSP memory */
- if ((fsp_memory != NULL) && (cbmem_root != NULL) &&
- (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) {
- fsp_verification_failure = 1;
- printk(BIOS_DEBUG,
- "ERROR - FSP reserved memory above CBMEM root!\n");
- }
-
- /* Verify that the FSP memory was properly reserved */
- if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) ||
- (fsp_memory->PhysicalStart !=
- (unsigned int)fsp_reserved_memory_area))) {
- fsp_verification_failure = 1;
- printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n");
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
- if (cbmem_root != NULL) {
- size_t delta_bytes = (unsigned int)smm_base
- - cbmem_root->PhysicalStart
- - cbmem_root->ResourceLength;
- printk(BIOS_DEBUG,
- "0x%08x: Chipset reserved bytes reported by FSP\n",
- (unsigned int)delta_bytes);
- die("Please verify the chipset reserved size\n");
- }
-#endif
- }
-
- /* Verify the FSP 1.1 HOB interface */
- if (fsp_verification_failure)
- die("ERROR - Coreboot's requirements not met by FSP binary!\n");
-
- /* Display the memory configuration */
- report_memory_config();
-
- /* Locate the memory configuration data to speed up the next reboot */
- mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr);
- if (mrc_hob == NULL)
- printk(BIOS_DEBUG,
- "Memory Configuration Data Hob not present\n");
- else {
- pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob);
- pei_ptr->data_to_save_size = ALIGN(
- ((u32)GET_HOB_LENGTH(mrc_hob)), 16);
- }
-}
-
-/* Initialize the UPD parameters for MemoryInit */
-__attribute__((weak)) void mainboard_memory_init_params(
- struct romstage_params *params,
- MEMORY_INIT_UPD *upd_ptr)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Display the UPD parameters for MemoryInit */
-__attribute__((weak)) void soc_display_memory_init_params(
- const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
-{
- printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
- hexdump32(BIOS_SPEW, new, sizeof(*new));
-}
-
-/* Initialize the UPD parameters for MemoryInit */
-__attribute__((weak)) void soc_memory_init_params(
- struct romstage_params *params,
- MEMORY_INIT_UPD *upd)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h
deleted file mode 100644
index d6cb895..0000000
--- a/src/soc/intel/common/ramstage.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _INTEL_COMMON_RAMSTAGE_H_
-#define _INTEL_COMMON_RAMSTAGE_H_
-
-#include <fsp/util.h>
-#include <soc/intel/common/util.h>
-#include <stdint.h>
-
-/* Perform Intel silicon init. */
-void intel_silicon_init(void);
-/* Called after the silicon init code has run. */
-void soc_after_silicon_init(void);
-/* Initialize UPD data before SiliconInit call. */
-void soc_silicon_init_params(SILICON_INIT_UPD *params);
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params);
-void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
- SILICON_INIT_UPD *new);
-void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params);
-
-#endif /* _INTEL_COMMON_RAMSTAGE_H_ */
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
deleted file mode 100644
index 6fc569c..0000000
--- a/src/soc/intel/common/romstage.c
+++ /dev/null
@@ -1,416 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <arch/io.h>
-#include <arch/cbfs.h>
-#include <arch/stages.h>
-#include <arch/early_variables.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <cbmem.h>
-#include <cpu/x86/mtrr.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <elog.h>
-#include <fsp/util.h>
-#include <memory_info.h>
-#include <reset.h>
-#include <romstage_handoff.h>
-#include <smbios.h>
-#include <soc/intel/common/mrc_cache.h>
-#include <soc/intel/common/util.h>
-#include <soc/pei_wrapper.h>
-#include <soc/pm.h>
-#include <soc/romstage.h>
-#include <soc/spi.h>
-#include <stage_cache.h>
-#include <timestamp.h>
-#include <tpm.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
-{
- void *top_of_stack;
- struct pei_data pei_data;
- struct romstage_params params = {
- .pei_data = &pei_data,
- .chipset_context = fih,
- };
-
- post_code(0x30);
-
- timestamp_add_now(TS_START_ROMSTAGE);
-
- memset(&pei_data, 0, sizeof(pei_data));
-
- /* Display parameters */
- printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
- CONFIG_MMCONF_BASE_ADDRESS);
- printk(BIOS_INFO, "Using: %s\n",
- IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) ? "FSP 1.1" :
- (IS_ENABLED(CONFIG_HAVE_MRC) ? "MRC" :
- "No Memory Support"));
-
- /* Display FSP banner */
- print_fsp_info(fih);
-
- /* Get power state */
- params.power_state = fill_power_state();
-
- /*
- * Read and print board version. Done after SOC romstage
- * in case PCH needs to be configured to talk to the EC.
- */
- if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
- printk(BIOS_INFO, "MLB: board version %d\n", board_id());
-
- /* Call into mainboard. */
- mainboard_romstage_entry(¶ms);
- soc_after_ram_init(¶ms);
- post_code(0x38);
-
- top_of_stack = setup_stack_and_mtrrs();
-
- printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
- timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START);
- return top_of_stack;
-}
-
-void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
-{
- return romstage_main(fih);
-}
-
-/* Entry from the mainboard. */
-void romstage_common(struct romstage_params *params)
-{
- const struct mrc_saved_data *cache;
- struct romstage_handoff *handoff;
- struct pei_data *pei_data;
-
- post_code(0x32);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- pei_data = params->pei_data;
- pei_data->boot_mode = params->power_state->prev_sleep_state;
-
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
- if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
- boot_count_increment();
-#endif
-
- /* Perform remaining SOC initialization */
- soc_pre_ram_init(params);
- post_code(0x33);
-
- /* Check recovery and MRC cache */
- params->pei_data->saved_data_size = 0;
- params->pei_data->saved_data = NULL;
- if (!params->pei_data->disable_saved_data) {
- if (recovery_mode_enabled()) {
- /* Recovery mode does not use MRC cache */
- printk(BIOS_DEBUG,
- "Recovery mode: not using MRC cache.\n");
- } else if (!mrc_cache_get_current(&cache)) {
- /* MRC cache found */
- params->pei_data->saved_data_size = cache->size;
- params->pei_data->saved_data = &cache->data[0];
- } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) {
- /* Waking from S3 and no cache. */
- printk(BIOS_DEBUG,
- "No MRC cache found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
- hard_reset();
- } else {
- printk(BIOS_DEBUG, "No MRC cache found.\n");
- mainboard_check_ec_image(params);
- }
- }
-
- /* Initialize RAM */
- raminit(params);
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Save MRC output */
- printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
- pei_data->data_to_save_size);
- if (params->pei_data->boot_mode != SLEEP_STATE_S3) {
- if (params->pei_data->data_to_save_size != 0 &&
- params->pei_data->data_to_save != NULL) {
- mrc_cache_stash_data(params->pei_data->data_to_save,
- params->pei_data->data_to_save_size);
- }
- }
-
- /* Save DIMM information */
- mainboard_save_dimm_info(params);
-
- /* Create romstage handof information */
- handoff = romstage_handoff_find_or_add();
- if (handoff != NULL)
- handoff->s3_resume = (params->power_state->prev_sleep_state ==
- SLEEP_STATE_S3);
- else {
- printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
- hard_reset();
- }
-
- if (IS_ENABLED(CONFIG_LPC_TPM))
- init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3);
-}
-
-void after_cache_as_ram_stage(void)
-{
- /* Load the ramstage. */
- copy_and_run();
- die("ERROR - Failed to load ramstage!");
-}
-
-/* Initialize the power state */
-__attribute__((weak)) struct chipset_power_state *fill_power_state(void)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
- return NULL;
-}
-
-__attribute__((weak)) void mainboard_check_ec_image(
- struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
- struct pei_data *pei_data;
-
- pei_data = params->pei_data;
- if (params->pei_data->boot_mode == SLEEP_STATE_S0) {
- /* Ensure EC is running RO firmware. */
- google_chromeec_check_ec_image(EC_IMAGE_RO);
- }
-#endif
-}
-
-/* Board initialization before and after RAM is enabled */
-__attribute__((weak)) void mainboard_romstage_entry(
- struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-
- post_code(0x31);
-
- /* Initliaze memory */
- romstage_common(params);
-}
-
-/* Save the DIMM information for SMBIOS table 17 */
-__attribute__((weak)) void mainboard_save_dimm_info(
- struct romstage_params *params)
-{
- int channel;
- CHANNEL_INFO *channel_info;
- int dimm;
- DIMM_INFO *dimm_info;
- int dimm_max;
- void *hob_list_ptr;
- EFI_HOB_GUID_TYPE *hob_ptr;
- int index;
- struct memory_info *mem_info;
- FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
- const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
-
- /* Locate the memory info HOB, presence validated by raminit */
- hob_list_ptr = fsp_get_hob_list();
- hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr);
- memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1);
-
- /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
- if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) {
- printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n");
- printk(BIOS_DEBUG, " 0x%02x: Revision\n",
- memory_info_hob->Revision);
- printk(BIOS_DEBUG, " 0x%02x: MemoryType\n",
- memory_info_hob->MemoryType);
- printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n",
- memory_info_hob->MemoryFrequencyInMHz);
- printk(BIOS_DEBUG, " %d: DataWidth in bits\n",
- memory_info_hob->DataWidth);
- printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n",
- memory_info_hob->ErrorCorrectionType);
- printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n",
- memory_info_hob->ChannelCount);
- for (channel = 0; channel < memory_info_hob->ChannelCount;
- channel++) {
- channel_info = &memory_info_hob->ChannelInfo[channel];
- printk(BIOS_DEBUG, " Channel %d\n", channel);
- printk(BIOS_DEBUG, " 0x%02x: ChannelId\n",
- channel_info->ChannelId);
- printk(BIOS_DEBUG, " 0x%02x: DimmCount\n",
- channel_info->DimmCount);
- for (dimm = 0; dimm < channel_info->DimmCount;
- dimm++) {
- dimm_info = &channel_info->DimmInfo[dimm];
- printk(BIOS_DEBUG, " DIMM %d\n", dimm);
- printk(BIOS_DEBUG, " 0x%02x: DimmId\n",
- dimm_info->DimmId);
- printk(BIOS_DEBUG, " %d: SizeInMb\n",
- dimm_info->SizeInMb);
- }
- }
- }
-
- /*
- * Allocate CBMEM area for DIMM information used to populate SMBIOS
- * table 17
- */
- mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
- printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
- if (mem_info == NULL)
- return;
- memset(mem_info, 0, sizeof(*mem_info));
-
- /* Describe the first N DIMMs in the system */
- index = 0;
- dimm_max = ARRAY_SIZE(mem_info->dimm);
- for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
- if (index >= dimm_max)
- break;
- channel_info = &memory_info_hob->ChannelInfo[channel];
- for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
- if (index >= dimm_max)
- break;
- dimm_info = &channel_info->DimmInfo[dimm];
-
- /* Populate the DIMM information */
- if (dimm_info->SizeInMb) {
- mem_info->dimm[index].dimm_size =
- dimm_info->SizeInMb;
- mem_info->dimm[index].ddr_type =
- memory_info_hob->MemoryType;
- mem_info->dimm[index].ddr_frequency =
- memory_info_hob->MemoryFrequencyInMHz;
- mem_info->dimm[index].channel_num =
- channel_info->ChannelId;
- mem_info->dimm[index].dimm_num =
- dimm_info->DimmId;
- switch (memory_info_hob->DataWidth) {
- default:
- case 8:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_8;
- break;
-
- case 16:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_16;
- break;
-
- case 32:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_32;
- break;
-
- case 64:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_64;
- break;
-
- case 128:
- mem_info->dimm[index].bus_width =
- MEMORY_BUS_WIDTH_128;
- break;
- }
-
- /* Add any mainboard specific information */
- mainboard_add_dimm_info(params, mem_info,
- channel, dimm, index);
- index++;
- }
- }
- }
- mem_info->dimm_cnt = index;
- printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
-}
-
-/* Add any mainboard specific information */
-__attribute__((weak)) void mainboard_add_dimm_info(
- struct romstage_params *params,
- struct memory_info *mem_info,
- int channel, int dimm, int index)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Get the memory configuration data */
-__attribute__((weak)) int mrc_cache_get_current(
- const struct mrc_saved_data **cache)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
- return -1;
-}
-
-/* Save the memory configuration data */
-__attribute__((weak)) int mrc_cache_stash_data(void *data, size_t size)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
- return -1;
-}
-
-/* Transition RAM from off or self-refresh to active */
-__attribute__((weak)) void raminit(struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
- post_code(0x34);
- die("ERROR - No RAM initialization specified!\n");
-}
-
-void ramstage_cache_invalid(void)
-{
- if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE))
- /* Perform cold reset on invalid ramstage cache. */
- hard_reset();
-}
-
-/* Display the memory configuration */
-__attribute__((weak)) void report_memory_config(void)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* Choose top of stack and setup MTRRs */
-__attribute__((weak)) void *setup_stack_and_mtrrs(void)
-{
- printk(BIOS_ERR, "WEAK: %s/%s called\n", __FILE__, __func__);
- die("ERROR - Must specify top of stack!\n");
- return NULL;
-}
-
-/* SOC initialization after RAM is enabled */
-__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* SOC initialization before RAM is enabled */
-__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
deleted file mode 100644
index 272679f..0000000
--- a/src/soc/intel/common/romstage.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _COMMON_ROMSTAGE_H_
-#define _COMMON_ROMSTAGE_H_
-
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <memory_info.h>
-#include <fsp/car.h>
-#include <fsp/util.h>
-#include <soc/intel/common/util.h>
-#include <soc/pei_data.h>
-#include <soc/pm.h> /* chip_power_state */
-
-struct romstage_params {
- unsigned long bist;
- struct chipset_power_state *power_state;
- struct pei_data *pei_data;
- void *chipset_context;
-};
-
-/*
- * FSP Boot Flow:
- * 1. src/cpu/x86/16bit/reset.inc
- * 2. src/cpu/x86/16bit/entry.inc
- * 3. other modules
- * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc
- * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp
- * 6. FSP binary/TempRamInit
- * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return
- * 8. src/soc/intel/common/romstage.c/romstage_main
- * 9 src/soc/.../romstage/.../soc_pre_console_init
- * 10 src/console/console.c/console_init
- * 11 src/soc/.../romstage/.../soc_romstage_init
- * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry
- * 13. src/soc/intel/common/romstage.c/romstage_common
- * 14 src/soc/.../romstage/.../soc_pre_raminit
- * 15. FSP binary/MemoryInit
- * 16. src/soc/intel/common/romstage.c/romstage_common - return
- * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return
- * 18. src/soc/intel/common/romstage.c/romstage_main - return
- * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs
- * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup
- * after call to romstage_main
- * 21. FSP binary/TempRamExit
- * 22. src/soc/intel/common/romstage.c/romstage_after_car
- * 23. FSP binary/SiliconInit
- * 24. src/soc/intel/common/romstage.c/romstage_after_car - return
- * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
- * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
- * 27. FSP binary/FspNotify
- * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback
- * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify
- * 30. FSP binary/FspNotify
- */
-
-void mainboard_check_ec_image(struct romstage_params *params);
-void mainboard_memory_init_params(struct romstage_params *params,
- MEMORY_INIT_UPD *memory_params);
-void mainboard_romstage_entry(struct romstage_params *params);
-void mainboard_save_dimm_info(struct romstage_params *params);
-void mainboard_add_dimm_info(struct romstage_params *params,
- struct memory_info *mem_info,
- int channel, int dimm, int index);
-void raminit(struct romstage_params *params);
-void report_memory_config(void);
-void romstage_common(struct romstage_params *params);
-asmlinkage void *romstage_main(FSP_INFO_HEADER *fih);
-void *setup_stack_and_mtrrs(void);
-void soc_after_ram_init(struct romstage_params *params);
-void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
- MEMORY_INIT_UPD *new);
-void soc_memory_init_params(struct romstage_params *params,
- MEMORY_INIT_UPD *upd);
-void soc_pre_ram_init(struct romstage_params *params);
-
-#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/soc/intel/common/stack.c b/src/soc/intel/common/stack.c
deleted file mode 100644
index 6cf03f2..0000000
--- a/src/soc/intel/common/stack.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <cbmem.h>
-#include <console/console.h>
-#include <cpu/x86/mtrr.h>
-#include "memmap.h"
-#include "romstage.h"
-#include <soc/intel/common/util.h>
-#include "stack.h"
-#include <stdlib.h>
-
-const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
-
-/*
- * Romstage needs quite a bit of stack for decompressing images since the lzma
- * lib keeps its state on the stack during romstage.
- */
-static unsigned long choose_top_of_stack(void)
-{
- unsigned long stack_top;
-
- /* cbmem_add() does a find() before add(). */
- stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
- romstage_ram_stack_size);
- stack_top += romstage_ram_stack_size;
- return stack_top;
-}
-
-/*
- * setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use.
- */
-void *setup_stack_and_mtrrs(void)
-{
- size_t alignment;
- uint32_t aligned_ram;
- uint32_t mtrr_mask_upper;
- uint32_t max_mtrrs;
- uint32_t num_mtrrs;
- uint32_t *slot;
- unsigned long top_of_stack;
-
- /* Display the MTTRs */
- soc_display_mtrrs();
-
- /* Top of stack needs to be aligned to a 8-byte boundary. */
- top_of_stack = choose_top_of_stack();
- slot = (void *)top_of_stack;
- num_mtrrs = 0;
- max_mtrrs = soc_get_variable_mtrr_count(NULL);
-
- /*
- * The upper bits of the MTRR mask need to set according to the number
- * of physical address bits.
- */
- mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
- alignment = mmap_region_granluarity();
- aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size,
- alignment);
-
- /*
- * The order for each MTRR is value then base with upper 32-bits of
- * each value coming before the lower 32-bits. The reasoning for
- * this ordering is to create a stack layout like the following:
- *
- * +36: MTRR mask 1 63:32
- * +32: MTRR mask 1 31:0
- * +28: MTRR base 1 63:32
- * +24: MTRR base 1 31:0
- * +20: MTRR mask 0 63:32
- * +16: MTRR mask 0 31:0
- * +12: MTRR base 0 63:32
- * +8: MTRR base 0 31:0
- * +4: Number of MTRRs to setup (described above)
- * +0: Number of variable MTRRs to clear
- */
-
- /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
- slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push32(slot, 0); /* upper base */
- slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
- /*
- * +-------------------------+ Top of RAM (aligned)
- * | System Management Mode |
- * | code and data | Length: CONFIG_TSEG_SIZE
- * | (TSEG) |
- * +-------------------------+ SMM base (aligned)
- * | |
- * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
- * | |
- * +-------------------------+ top_of_ram (aligned)
- * | |
- * | CBMEM Root |
- * | |
- * +-------------------------+
- * | |
- * | FSP Reserved Memory |
- * | |
- * +-------------------------+
- * | |
- * | Various CBMEM Entries |
- * | |
- * +-------------------------+ top_of_stack (8 byte aligned)
- * | |
- * | stack (CBMEM Entry) |
- * | |
- * +-------------------------+
- */
-
- /*
- * Cache the stack and the other CBMEM entries as well as part or all
- * of the FSP reserved memory region.
- */
- slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push32(slot, 0); /* upper base */
- slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
- void *smm_base;
- size_t smm_size;
- uint32_t tseg_base;
-
- /*
- * Cache the TSEG region at the top of ram. This region is not
- * restricted to SMM mode until SMM has been relocated. By setting
- * the region to cacheable it provides faster access when relocating
- * the SMM handler as well as using the TSEG region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- tseg_base = (uint32_t)smm_base;
- slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push32(slot, 0); /* upper base */
- slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-#endif
-
- /* Cache the ROM as WP just below 4GiB. */
- slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push32(slot, 0); /* upper base */
- slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
- num_mtrrs++;
-
- /* Validate the MTRR usage */
- if (num_mtrrs > max_mtrrs) {
- printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d",
- max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs);
- die("ERROR - MTRR use count incorrect!\n");
- }
-
- /*
- * Save the number of MTRRs to setup and clear. Return the stack
- * location pointing to the number of MTRRs.
- */
- slot = stack_push32(slot, num_mtrrs);
- slot = stack_push32(slot, max_mtrrs);
- return slot;
-}
-
diff --git a/src/soc/intel/common/stack.h b/src/soc/intel/common/stack.h
deleted file mode 100644
index f5333a7..0000000
--- a/src/soc/intel/common/stack.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _COMMON_STACK_H_
-#define _COMMON_STACK_H_
-
-#include <stdint.h>
-
-static inline void *stack_push32(void *stack, uint32_t value)
-{
- uint32_t *stack32 = stack;
-
- stack32 = &stack32[-1];
- *stack32 = value;
- return stack32;
-}
-
-#endif /* _COMMON_STACK_H_ */
diff --git a/src/soc/intel/common/stage_cache.c b/src/soc/intel/common/stage_cache.c
deleted file mode 100644
index 5bb83c9..0000000
--- a/src/soc/intel/common/stage_cache.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <console/console.h>
-#include <soc/intel/common/memmap.h>
-#include <stage_cache.h>
-
-void stage_cache_external_region(void **base, size_t *size)
-{
- if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
- printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
- *size = 0;
- }
-}
diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c
index 591c100..a886c7c 100644
--- a/src/soc/intel/common/util.c
+++ b/src/soc/intel/common/util.c
@@ -24,52 +24,6 @@
#include <soc/intel/common/util.h>
#include <stddef.h>
-void soc_display_upd_value(const char *name, uint32_t size, uint64_t old,
- uint64_t new)
-{
- if (old == new) {
- switch (size) {
- case 1:
- printk(BIOS_SPEW, " 0x%02llx: %s\n", new, name);
- break;
-
- case 2:
- printk(BIOS_SPEW, " 0x%04llx: %s\n", new, name);
- break;
-
- case 4:
- printk(BIOS_SPEW, " 0x%08llx: %s\n", new, name);
- break;
-
- case 8:
- printk(BIOS_SPEW, " 0x%016llx: %s\n", new, name);
- break;
- }
- } else {
- switch (size) {
- case 1:
- printk(BIOS_SPEW, " 0x%02llx --> 0x%02llx: %s\n", old,
- new, name);
- break;
-
- case 2:
- printk(BIOS_SPEW, " 0x%04llx --> 0x%04llx: %s\n", old,
- new, name);
- break;
-
- case 4:
- printk(BIOS_SPEW, " 0x%08llx --> 0x%08llx: %s\n", old,
- new, name);
- break;
-
- case 8:
- printk(BIOS_SPEW, " 0x%016llx --> 0x%016llx: %s\n",
- old, new, name);
- break;
- }
- }
-}
-
uint32_t soc_get_variable_mtrr_count(uint64_t *msr)
{
union {
diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h
index de5e0a0..8790b97 100644
--- a/src/soc/intel/common/util.h
+++ b/src/soc/intel/common/util.h
@@ -24,8 +24,6 @@
#include <stdint.h>
asmlinkage void soc_display_mtrrs(void);
-void soc_display_upd_value(const char *name, uint32_t size, uint64_t old,
- uint64_t new);
uint32_t soc_get_variable_mtrr_count(uint64_t *msr);
#endif /* _INTEL_COMMON_UTIL_H_ */
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
deleted file mode 100644
index 3aba7c7..0000000
--- a/src/soc/intel/common/vbt.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <fsp/util.h>
-#include <lib.h>
-#include <soc/intel/common/ramstage.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-/* Locate VBT and pass it to FSP GOP */
-void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
-{
- const optionrom_vbt_t *vbt_data;
- uint32_t vbt_len;
-
- /* Check boot mode - for S3 resume path VBT loading is not needed */
- if (s3_resume) {
- vbt_data = NULL;
- printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n");
- } else {
- if (developer_mode_enabled() || recovery_mode_enabled()) {
- /* Get VBT data */
- vbt_data = fsp_get_vbt(&vbt_len);
- if (vbt_data != NULL)
- printk(BIOS_DEBUG, "Passing VBT to GOP\n");
- else
- printk(BIOS_DEBUG, "VBT not found!\n");
- } else
- vbt_data = NULL;
- }
- params->GraphicsConfigPtr = (u32)vbt_data;
-}
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 2ea20a0..d63fa70 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -19,6 +19,10 @@ config CPU_SPECIFIC_OPTIONS
select COLLECT_TIMESTAMPS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_MICROCODE_IN_CBFS
+ select FSP_RAM_INIT
+ select FSP_ROMSTAGE
+ select FSP_STACK
+ select FSP_STAGE_CACHE
select GENERIC_GPIO_LIB
select HAS_PRECBMEM_TIMESTAMP_REGION
select HAVE_HARD_RESET
@@ -39,11 +43,7 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
- select SOC_INTEL_COMMON_FSP_RAM_INIT
- select SOC_INTEL_COMMON_FSP_ROMSTAGE
select SOC_INTEL_COMMON_RESET
- select SOC_INTEL_COMMON_STACK
- select SOC_INTEL_COMMON_STAGE_CACHE
select SMM_MODULES
select SMM_TSEG
select SMP
diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h
index fb06b33..5c10393 100644
--- a/src/soc/intel/skylake/include/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/soc/ramstage.h
@@ -23,7 +23,7 @@
#include <chip.h>
#include <device/device.h>
-#include <soc/intel/common/ramstage.h>
+#include <fsp/ramstage.h>
void pch_enable_dev(device_t dev);
void soc_init_pre_device(void *chip_info);
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index a88de66..1d42548 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -21,7 +21,7 @@
#ifndef _SOC_ROMSTAGE_H_
#define _SOC_ROMSTAGE_H_
-#include <soc/intel/common/romstage.h>
+#include <fsp/romstage.h>
struct chipset_power_state;
struct chipset_power_state *fill_power_state(void);
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index 212a444..5f5167d 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -23,8 +23,8 @@
#include <stdint.h>
#include <cpu/x86/msr.h>
-#include <soc/intel/common/romstage.h>
-#include <soc/intel/common/memmap.h>
+#include <fsp/memmap.h>
+#include <fsp/romstage.h>
#include <soc/gpio.h>
struct ied_header {
diff --git a/src/soc/intel/skylake/ramstage.c b/src/soc/intel/skylake/ramstage.c
index 3646843..e215978 100644
--- a/src/soc/intel/skylake/ramstage.c
+++ b/src/soc/intel/skylake/ramstage.c
@@ -19,7 +19,6 @@
*/
#include <soc/ramstage.h>
-#include <soc/intel/common/ramstage.h>
void soc_init_pre_device(void *chip_info)
{
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