[coreboot-gerrit] New patch to review for coreboot: intel/kunimitsu FAB3: Configure LPC to Quiet Mode.

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12153

-gerrit

commit 26ae45a55c453595a4c52eea86dfc9a39f7e3565
Author: pchandri <preetham.chandrian at intel.com>
Date:   Wed Sep 9 17:22:09 2015 -0700

    intel/kunimitsu FAB3: Configure LPC to Quiet Mode.
    
    This patch configures the LPC to quiet mode and sets
    enables CLKRUN so that LPC can be power gated.
    
    BUG=chrome-os-partner:44993
    BRANCH=none
    TEST=Builds and Boots on fab3 kunimitsu.
    
    Change-Id: I46ff21f75b70f54da3f12dcc56d61f84b436cd7d
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: edd37df385bc013b62f26435267291acc0a9b9a4
    Original-Change-Id: Ide0f9e91127aebb8ac027ee0a598608b50aa4278
    Original-Signed-off-by: pchandri <preetham.chandrian at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/305396
    Original-Commit-Ready: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Tested-by: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-by: Preetham Chandrian <preetham.chandrian at intel.com>
---
 src/soc/intel/skylake/Kconfig           | 2 +-
 src/soc/intel/skylake/include/soc/lpc.h | 2 ++
 src/soc/intel/skylake/lpc.c             | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 1f42927..2ea20a0 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -119,7 +119,7 @@ config SERIAL_CPU_INIT
 
 config SERIRQ_CONTINUOUS_MODE
 	bool
-	default y
+	default n
 	help
 	  If you set this option to y, the serial IRQ machine will be
 	  operated in continuous mode.
diff --git a/src/soc/intel/skylake/include/soc/lpc.h b/src/soc/intel/skylake/include/soc/lpc.h
index 4e826d7..63ffa16 100644
--- a/src/soc/intel/skylake/include/soc/lpc.h
+++ b/src/soc/intel/skylake/include/soc/lpc.h
@@ -54,4 +54,6 @@
 #define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
 #define LGMR			0x98 /* LPC Generic Memory Range */
 #define BIOS_CNTL		0xdc
+#define PCCTL			0xE0 /* PCI Clock Control */
+#define CLKRUN_EN		(1 << 0)
 #endif
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index 861b5ba..f612fda 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -153,6 +153,8 @@ static const struct reg_script pch_misc_init_script[] = {
 #if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
 	REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
 #endif
+	/* Enable CLKRUN_EN for power gating LPC */
+	REG_PCI_OR8(PCCTL, (CLKRUN_EN)),
 	REG_SCRIPT_END
 };