[coreboot-gerrit] New patch to review for coreboot: google/glados: Add USB phy settings and update enabled options

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12149

-gerrit

commit 91580efe59a41bcb832e162d760a66bec25911c7
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Oct 9 09:23:33 2015 -0700

    google/glados: Add USB phy settings and update enabled options
    
    - Add placeholder USB phy settings, needs tuning still
    - Change UART2 to be skipped during FSP init
    - Update headphone codec irq to be level triggered as
    that is how the kernel is configuring it
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I9a15a27dab49d4e19f8ef0574ee2e61ae90c99fc
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6e7a0032ba23d6762342639c2c7cb877c1f90452
    Original-Change-Id: Ie1439f21116022b0644d06853df9490e4651a9ae
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/304926
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/acpi/mainboard.asl |  2 +-
 src/mainboard/google/glados/devicetree.cb      | 39 +++++++++++++++++++++++++-
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl
index b449ec4..a292f46 100644
--- a/src/mainboard/google/glados/acpi/mainboard.asl
+++ b/src/mainboard/google/glados/acpi/mainboard.asl
@@ -189,7 +189,7 @@ Scope (\_SB.PCI0.I2C4)
 				AddressingMode7Bit,
 				"\\_SB.PCI0.I2C4",
 			)
-			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			Interrupt (ResourceConsumer, Level, ActiveLow)
 			{
 				BOARD_HP_MIC_CODEC_IRQ
 			}
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index e57c490..797865d 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -65,6 +65,43 @@ chip soc/intel/skylake
 	register "PortUsb30Enable[2]" = "1"	# Type-A Port 1
 	register "PortUsb30Enable[3]" = "1"	# Type-A Port 2
 
+	# USB Per Port HS Preemphasis Bias
+	register "Usb2AfePetxiset" = "{ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
+					0x07, 0x07, 0x07, 0x07, 0x07, 0x07, \
+					0x07, 0x07, 0x07, 0x07 }"
+
+	# USB Per Port HS Transmitter Bias
+	register "Usb2AfeTxiset" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+				      0x00, 0x00, 0x05, 0x00, 0x00, 0x00, \
+				      0x00, 0x00, 0x00, 0x00 }"
+
+	# USB Per Port HS Transmitter Emphasis
+	register "Usb2AfePredeemp" = "{ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, \
+					0x02, 0x02, 0x02, 0x02, 0x03, 0x03, \
+					0x03, 0x03, 0x03, 0x03 }"
+
+	# USB Per Port Half Bit Pre-emphasis
+	register "Usb2AfePehalfbit" = "{ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, \
+					 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, \
+					 0x00, 0x00, 0x00, 0x00 }"
+
+	# Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+	register "Usb3HsioTxDeEmphEnable" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
+					       0x00, 0x00, 0x00, 0x00, 0x00 }"
+
+	# USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+	register "Usb3HsioTxDeEmph" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
+					 0x00, 0x00, 0x00, 0x00, 0x00 }"
+
+	# Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+	register "Usb3HsioTxDownscaleAmpEnable" = "{ 0x00, 0x00, 0x00, 0x00, \
+						     0x00, 0x00, 0x00, 0x00, \
+						     0x00, 0x00 }"
+
+	# USB 3.0 TX Output Downscale Amplitude Adjustment
+	register "Usb3HsioTxDownscaleAmp" = "{ 0x00, 0x00, 0x00, 0x00, 0x00, \
+					       0x00, 0x00, 0x00, 0x00, 0x00 }"
+
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{ \
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
@@ -77,7 +114,7 @@ chip soc/intel/skylake
 		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
 		[PchSerialIoIndexUart0] = PchSerialIoPci, \
 		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
-		[PchSerialIoIndexUart2] = PchSerialIoPci, \
+		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 	}"
 
 	device cpu_cluster 0 on