[coreboot-gerrit] New patch to review for coreboot: intel/kunimitsu: USB Phy settings and Skip UART2 init in FSP

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12145

-gerrit

commit 37e19ca16297b878fae2b3597134262b93af89da
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Mon Oct 5 19:13:01 2015 +0530

    intel/kunimitsu: USB Phy settings and Skip UART2 init in FSP
    
    FSP 1.7.0 provides UPD to configure USB phy settings
    update the same for kunimitsu.
    
    FSP 1.7.0 also provides UPD to indicate FSP not to reinitialise
    UART2 controller during MemoryInit.
    
    BRANCH=none
    BUG=chrome-os-partner:45684,chrome-os-partner:41374,chrome-os-partner:42284
    TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB,
    	Boot from eMMC, USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume
    
    CQ-DEPEND=CL:303661
    
    Change-Id: Ie0a545c954f472cc822b63786d40399ec93d5166
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 90296e04942c70d972c225fc75dfab6de44d10ed
    Original-Change-Id: If79e81ef3323e782e96db307d89a01c14174b435
    Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/304032
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/devicetree.cb | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 21af62a..dfba699 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -60,11 +60,29 @@ chip soc/intel/skylake
 	register "PortUsb20Enable[6]" = "1"	# Camera
 	register "PortUsb20Enable[8]" = "1"	# Type-A Port (board)
 
+	#USB Per Port HS Preemphasis Bias
+        register "Usb2AfePetxiset" = "{0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}"
+	#USB Per Port HS Transmitter Bias
+        register "Usb2AfeTxiset" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
+        #USB Per Port HS Transmitter Emphasis
+	register "Usb2AfePredeemp" = "{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}"
+	#USB Per Port Half Bit Pre-emphasis
+        register "Usb2AfePehalfbit" = "{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
+
 	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
 	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
 	register "PortUsb30Enable[2]" = "1"	# Type-A Port (card)
 	register "PortUsb30Enable[3]" = "1"	# Type-A Port (board)
 
+	#Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+        register "Usb3HsioTxDeEmphEnable" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
+	#USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+        register "Usb3HsioTxDeEmph" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
+	#Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+        register "Usb3HsioTxDownscaleAmpEnable" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
+	#USB 3.0 TX Output Downscale Amplitude Adjustment
+        register "Usb3HsioTxDownscaleAmp" = "{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}"
+
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{ \
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
@@ -77,7 +95,7 @@ chip soc/intel/skylake
 		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
 		[PchSerialIoIndexUart0] = PchSerialIoPci, \
 		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
-		[PchSerialIoIndexUart2] = PchSerialIoPci, \
+		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
 	}"
 
 	device cpu_cluster 0 on