[coreboot-gerrit] New patch to review for coreboot: google/veyron_rialto: Throttle to 1416MHz @ 1200mV in bootblock

Patrick Georgi (pgeorgi@google.com) gerrit at coreboot.org
Fri Oct 23 13:25:43 CEST 2015


Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12137

-gerrit

commit 2904f816d1d9189033885702d3091630158bb379
Author: David Hendricks <dhendrix at chromium.org>
Date:   Fri Sep 25 15:21:35 2015 -0700

    google/veyron_rialto: Throttle to 1416MHz @ 1200mV in bootblock
    
    The 1392MHz value used to throttle the RK3288 earlier was somewhat
    arbitrary. This patch brings the throttling in sync with the operating
    points specified in the Linux device tree for RK3288.
    
    BUG=chrome-os-partner:42054
    BRANCH=none
    TEST=Saw print statement in image.serial.bin indicating that APLL
    was set to the desired frequency.
    
    Change-Id: Ibe570267bbfe23f010ad5e1ea651356291b9c63c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a146f23b13cb0f6da93ada65648cf33ecfaaa7d6
    Original-Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Original-Change-Id: I6bcdb5fd6ffa3f9a22e79c519bdb7980492e2318
    Original-Reviewed-on: https://chromium-review.googlesource.com/302633
---
 src/mainboard/google/veyron_rialto/bootblock.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index a539c08..e87d8d1 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -63,9 +63,7 @@ void bootblock_mainboard_init(void)
 	/* Slowly raise to max CPU voltage to prevent overshoot */
 	rk808_configure_buck(1, 1200);
 	udelay(175);/* Must wait for voltage to stabilize,2mV/us */
-	rk808_configure_buck(1, 1400);
-	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
-	rkclk_configure_cpu(APLL_1392_MHZ);
+	rkclk_configure_cpu(APLL_1416_MHZ);
 
 	/* i2c1 for tpm */
 	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);



More information about the coreboot-gerrit mailing list