[coreboot-gerrit] Patch set updated for coreboot: intel/fsp1_0: Use dummy microcode when calling FSP TempRamInit

[York Yang (york.yang@intel.com)]

York Yang (york.yang at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11895

-gerrit

commit bc8acd8270cbf12c8d4603d196eda182daf71460
Author: York Yang <york.yang at intel.com>
Date:   Wed Oct 14 06:52:32 2015 -0700

    intel/fsp1_0: Use dummy microcode when calling FSP TempRamInit
    
    Pass in dummy microcode when calling FSP TempRamInit API. FSP will not
    do the microcode load and leave the work to coreboot.
    Ensure that BSP has been loaded a microcode before calling TempRamInit
    API, otherwise FSP will return error that No Valid Microcode Was Found.
    Change has been verified on fsp_baytrail and will be applied to rangeley.
    
    Change-Id: I8247c0503c8eb3d1c8eaa059632fb3a11c9daae9
    Signed-off-by: York Yang <york.yang at intel.com>
---
 src/drivers/intel/fsp1_0/Makefile.inc     | 11 -----------
 src/drivers/intel/fsp1_0/cache_as_ram.inc | 12 +++++-------
 2 files changed, 5 insertions(+), 18 deletions(-)

diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index deae45b..5899362 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -25,17 +25,6 @@ romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 
 CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
 
-ifneq ($(cpu_microcode_bins),)
-$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin
-	printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \
-	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
-else
-$(objgenerated)/microcode_size.h:
-	printf "#define MICROCODE_REGION_LENGTH 0" > $@.tmp \
-	&& cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@
-endif
-
-cpu_incs-$(CONFIG_PLATFORM_USES_FSP1_0) += $(objgenerated)/microcode_size.h
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
 
 ifeq ($(CONFIG_HAVE_FSP_BIN),y)
diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc
index d1167b1..5c24008 100644
--- a/src/drivers/intel/fsp1_0/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -22,17 +22,12 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <microcode_size.h>
 #include <cbmem.h>
 
 #ifndef CONFIG_FSP_LOC
 # error "CONFIG_FSP_LOC must be set."
 #endif
 
-#ifndef CONFIG_CPU_MICROCODE_CBFS_LOC
-# error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set."
-#endif
-
 	cmp   $0, %eax
 	je    cache_as_ram
 	mov   $0xa0, %eax
@@ -124,11 +119,14 @@ fake_fsp_stack:
 	.long  find_fsp_ret
 
 CAR_init_params:
-	.long  CONFIG_CPU_MICROCODE_CBFS_LOC
-	.long  MICROCODE_REGION_LENGTH
+	.long  dummy_microcode
+	.long  0
 	.long  0xFFFFFFFF - CACHE_ROM_SIZE + 1	/* Firmware Location */
 	.long  CACHE_ROM_SIZE	/* Total Firmware Length */
 
 CAR_init_stack:
 	.long  CAR_init_done
 	.long  CAR_init_params
+
+dummy_microcode:
+	.long  0