[coreboot-gerrit] Patch set updated for coreboot: southbridge/amd/sr5650: Use correct PCI configuration block offset

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12049

-gerrit

commit 312c08d1a1ccd92cacf24e8b0ae05926be0bc5bd
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Fri Aug 14 02:50:44 2015 -0500

    southbridge/amd/sr5650: Use correct PCI configuration block offset
    
    Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl
index a6ab114..1e0d5b0 100644
--- a/src/southbridge/amd/sr5650/acpi/sr5650.asl
+++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl
@@ -19,8 +19,8 @@
  */
 
 Scope(\) {
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
-	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)			/* Base address of HPET table */
 
 	/* PIC IRQ mapping registers, C00h-C01h */
 	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)