[coreboot-gerrit] New patch to review for coreboot: arm64: tegra132: tegra210: Remove old arm64/stage_entry.S
Julius Werner (jwerner@chromium.org)
gerrit at coreboot.org
Sat Oct 17 09:35:44 CEST 2015
Julius Werner (jwerner at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12078
-gerrit
commit dd01aa0ee4b0bb4387d664a5232da0fb48cea708
Author: Julius Werner <jwerner at chromium.org>
Date: Fri Oct 16 13:10:02 2015 -0700
arm64: tegra132: tegra210: Remove old arm64/stage_entry.S
This patch removes the old arm64/stage_entry.S code that was too
specific to the Tegra SoC boot flow, and replaces it with code that
hides the peculiarities of switching to a different CPU/arch in ramstage
in the Tegra SoC directories. Also removes some more remaining vestiges
of SMP support from arm64 architecture files.
BRANCH=None
BUG=None
TEST=Built Ryu and Smaug. !!!UNTESTED!!!
Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698
Signed-off-by: Julius Werner <jwerner at chromium.org>
---
src/arch/arm64/Kconfig | 1 -
src/arch/arm64/Makefile.inc | 14 +--
src/arch/arm64/armv8/exception.c | 7 +-
src/arch/arm64/c_entry.c | 133 -----------------------
src/arch/arm64/cpu-internal.h | 29 -----
src/arch/arm64/cpu-stubs.c | 25 -----
src/arch/arm64/cpu/Kconfig | 23 ----
src/arch/arm64/cpu/Makefile.inc | 24 ----
src/arch/arm64/cpu/cortex_a57.S | 29 -----
src/arch/arm64/include/arch/smc.h | 122 ---------------------
src/arch/arm64/include/arch/startup.h | 48 --------
src/arch/arm64/include/armv8/arch/cpu.h | 12 --
src/arch/arm64/include/armv8/arch/exception.h | 1 -
src/arch/arm64/include/armv8/arch/lib_helpers.h | 8 +-
src/arch/arm64/include/armv8/arch/smp/spinlock.h | 29 -----
src/arch/arm64/startup.c | 57 ----------
src/arch/arm64/transition.c | 41 ++++---
src/soc/nvidia/tegra132/Kconfig | 9 --
src/soc/nvidia/tegra132/Makefile.inc | 1 +
src/soc/nvidia/tegra132/maincpu.S | 55 ----------
src/soc/nvidia/tegra132/ramstage.c | 5 +
src/soc/nvidia/tegra132/stage_entry.S | 34 ++++++
src/soc/nvidia/tegra210/Kconfig | 10 --
src/soc/nvidia/tegra210/cpu.c | 2 +-
src/soc/nvidia/tegra210/maincpu.S | 55 ----------
src/soc/nvidia/tegra210/ramstage.c | 10 +-
src/soc/nvidia/tegra210/stage_entry.S | 18 ++-
27 files changed, 91 insertions(+), 711 deletions(-)
diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig
index 9b06589..21bbc9b 100644
--- a/src/arch/arm64/Kconfig
+++ b/src/arch/arm64/Kconfig
@@ -20,7 +20,6 @@ config ARCH_RAMSTAGE_ARM64
default n
source src/arch/arm64/armv8/Kconfig
-source src/arch/arm64/cpu/Kconfig
config ARM64_USE_ARM_TRUSTED_FIRMWARE
bool
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index c63786f..e7ec0d6 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -27,7 +27,7 @@
# Take care of subdirectories
################################################################################
-subdirs-y += armv8/ cpu/
+subdirs-y += armv8/
################################################################################
# ARM specific options
@@ -48,8 +48,6 @@ bootblock-y += id.S
$(obj)/arch/arm64/id.bootblock.o: $(obj)/build.h
bootblock-y += boot.c
-bootblock-y += c_entry.c
-bootblock-y += cpu-stubs.c
bootblock-y += eabi_compat.c
bootblock-y += transition.c transition_asm.S
@@ -91,8 +89,6 @@ endif # CONFIG_ARCH_VERSTAGE_ARM64
ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y)
romstage-y += boot.c
-romstage-y += c_entry.c
-romstage-y += cpu-stubs.c
romstage-y += div0.c
romstage-y += eabi_compat.c
romstage-y += memset.S
@@ -117,8 +113,6 @@ endif # CONFIG_ARCH_ROMSTAGE_ARM64
ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y)
-ramstage-y += c_entry.c
-ramstage-y += startup.c
ramstage-y += div0.c
ramstage-y += eabi_compat.c
ramstage-y += boot.c
@@ -126,15 +120,9 @@ ramstage-y += tables.c
ramstage-y += memset.S
ramstage-y += memcpy.S
ramstage-y += memmove.S
-ramstage-y += cpu-stubs.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c
ramstage-y += transition.c transition_asm.S
-# TODO: Replace this with a simpler ramstage entry point in soc/nvidia/tegra*
-ifeq ($(CONFIG_SOC_NVIDIA_TEGRA132)$(CONFIG_SOC_NVIDIA_TEGRA210),y)
-ramstage-y += stage_entry.S
-endif
-
rmodules_arm64-y += memset.S
rmodules_arm64-y += memcpy.S
rmodules_arm64-y += memmove.S
diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c
index ed6be7f..9a68341 100644
--- a/src/arch/arm64/armv8/exception.c
+++ b/src/arch/arm64/armv8/exception.c
@@ -164,15 +164,10 @@ void exc_dispatch(struct exc_state *state, uint64_t idx)
exc_exit(&state->regs);
}
-void exception_hwinit(void)
-{
- exc_set_vbar();
-}
-
void exception_init(void)
{
/* Load the exception table. */
- exception_hwinit();
+ exc_set_vbar();
printk(BIOS_DEBUG, "ARM64: Exception handlers installed.\n");
}
diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c
deleted file mode 100644
index 34f0646..0000000
--- a/src/arch/arm64/c_entry.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/cpu.h>
-#include <arch/lib_helpers.h>
-#include <arch/mmu.h>
-#include <arch/stages.h>
-#include <arch/startup.h>
-#include <gic.h>
-
-#include "cpu-internal.h"
-
-void __attribute__((weak)) arm64_soc_init(void)
-{
- /* Default weak implementation does nothing. */
-}
-
-static void seed_stack(void)
-{
- char *stack_begin;
- uint64_t *slot;
- int i;
- int size;
-
- stack_begin = cpu_get_stack();
- stack_begin -= CONFIG_STACK_SIZE;
- slot = (void *)stack_begin;
-
- /* Pad out 256 bytes for current usage. */
- size = CONFIG_STACK_SIZE - 256;
- size /= sizeof(*slot);
- for (i = 0; i < size; i++)
- *slot++ = 0xdeadbeefdeadbeefULL;
-}
-
-/* Set up default SCR values. */
-static void el3_init(void)
-{
- uint32_t scr;
-
- if (get_current_el() != EL3)
- return;
-
- scr = raw_read_scr_el3();
- /* Default to non-secure EL1 and EL0. */
- scr &= ~(SCR_NS_MASK);
- scr |= SCR_NS_ENABLE;
- /* Disable IRQ, FIQ, and external abort interrupt routing. */
- scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK);
- scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE;
- /* Enable HVC */
- scr &= ~(SCR_HVC_MASK);
- scr |= SCR_HVC_ENABLE;
- /* Disable SMC */
- scr &= ~(SCR_SMC_MASK);
- scr |= SCR_SMC_DISABLE;
- /* Disable secure instruction fetches. */
- scr &= ~(SCR_SIF_MASK);
- scr |= SCR_SIF_DISABLE;
- /* All lower exception levels 64-bit by default. */
- scr &= ~(SCR_RW_MASK);
- scr |= SCR_LOWER_AARCH64;
- /* Disable secure EL1 access to secure timer. */
- scr &= ~(SCR_ST_MASK);
- scr |= SCR_ST_DISABLE;
- /* Don't trap on WFE or WFI instructions. */
- scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK);
- scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE;
- raw_write_scr_el3(scr);
- isb();
-}
-
-void __attribute__((weak)) arm64_arch_timer_init(void)
-{
- /* Default weak implementation does nothing. */
-}
-
-static void arm64_init(void)
-{
- seed_stack();
-
- /* Set up default SCR values. */
- el3_init();
-
- /* Initialize the GIC. */
- gic_init();
-
- /*
- * Disable coprocessor traps to EL3:
- * TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR
- * and EL2/EL1 access to CPACR_EL1.
- * TTA [20] = 0, disable traps for trace register access from any EL.
- * TFP [10] = 0, disable traps for floating-point instructions from any
- * EL.
- */
- raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE |
- CPTR_EL3_TFP_DISABLE);
-
- /*
- * Allow FPU accesses:
- * FPEN [21:20] = 3, disable traps for floating-point instructions from
- * EL0/EL1.
- * TTA [28] = 0, disable traps for trace register access from EL0/EL1.
- */
- raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE);
-
- /* Arch Timer init: setup cntfrq per CPU */
- arm64_arch_timer_init();
-
- arm64_soc_init();
-
- main();
-}
-
-/* This variable holds entry point for CPU starting up. */
-void (*c_entry)(void) = &arm64_init;
diff --git a/src/arch/arm64/cpu-internal.h b/src/arch/arm64/cpu-internal.h
deleted file mode 100644
index 32a40fc..0000000
--- a/src/arch/arm64/cpu-internal.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef ARCH_CPU_INTERNAL_H
-#define ARCH_CPU_INTERNAL_H
-
-/* Return the top of the stack for the cpu. */
-void *cpu_get_stack(void);
-
-/* Return the top of the exception stack for the cpu. */
-void *cpu_get_exception_stack(void);
-
-#endif /* ARCH_CPU_INTERNAL_H */
diff --git a/src/arch/arm64/cpu-stubs.c b/src/arch/arm64/cpu-stubs.c
deleted file mode 100644
index 5372355..0000000
--- a/src/arch/arm64/cpu-stubs.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-void arm64_cpu_early_setup(void);
-
-void __attribute__((weak)) arm64_cpu_early_setup(void)
-{
- /* Default empty implementation */
-}
diff --git a/src/arch/arm64/cpu/Kconfig b/src/arch/arm64/cpu/Kconfig
deleted file mode 100644
index e1d65a7..0000000
--- a/src/arch/arm64/cpu/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2015 Google Inc
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-config ARCH_ARM64_CPU_CORTEX_A57
- bool
- default n
- depends on ARCH_ARM64
diff --git a/src/arch/arm64/cpu/Makefile.inc b/src/arch/arm64/cpu/Makefile.inc
deleted file mode 100644
index ebcd650..0000000
--- a/src/arch/arm64/cpu/Makefile.inc
+++ /dev/null
@@ -1,24 +0,0 @@
-################################################################################
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-################################################################################
-
-ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y)
-ramstage-$(CONFIG_ARCH_ARM64_CPU_CORTEX_A57) += cortex_a57.S
-endif
diff --git a/src/arch/arm64/cpu/cortex_a57.S b/src/arch/arm64/cpu/cortex_a57.S
deleted file mode 100644
index 37af059..0000000
--- a/src/arch/arm64/cpu/cortex_a57.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/asm.h>
-#include <cpu/cortex_a57.h>
-
-ENTRY(arm64_cpu_early_setup)
- mrs x0, CPUECTLR_EL1
- orr x0, x0, #(1 << SMPEN_SHIFT)
- msr CPUECTLR_EL1, x0
- isb
- ret
-ENDPROC(arm64_cpu_early_setup)
diff --git a/src/arch/arm64/include/arch/smc.h b/src/arch/arm64/include/arch/smc.h
deleted file mode 100644
index 4e1d7e4..0000000
--- a/src/arch/arm64/include/arch/smc.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __ARCH_SMC_H__
-#define __ARCH_SMC_H__
-
-#include <stdint.h>
-
-enum {
- FUNC_ID_CALL_TYPE_SHIFT = 31,
- FUNC_ID_CALL_TYPE_MASK = (1 << FUNC_ID_CALL_TYPE_SHIFT),
- FUNC_ID_FASTCALL = (1 << FUNC_ID_CALL_TYPE_SHIFT),
- FUNC_ID_STDCALL = (0 << FUNC_ID_CALL_TYPE_SHIFT),
-
- FUNC_ID_CALL_CONVENTION_SHIFT = 30,
- FUNC_ID_CALL_CONVENTION_MASK = (1 << FUNC_ID_CALL_CONVENTION_SHIFT),
- FUNC_ID_SMC32 = (0 << FUNC_ID_CALL_CONVENTION_SHIFT),
- FUNC_ID_SMC64 = (1 << FUNC_ID_CALL_CONVENTION_SHIFT),
-
- FUNC_ID_ENTITY_SHIFT = 24,
- FUNC_ID_ENTITY_MASK = (0x3f << FUNC_ID_ENTITY_SHIFT),
-
- FUNC_ID_FUNC_NUMBER_SHIFT = 0,
- FUNC_ID_FUNC_NUMBER_MASK = (0xffff << FUNC_ID_FUNC_NUMBER_SHIFT),
-
- FUNC_ID_MASK = FUNC_ID_CALL_TYPE_MASK | FUNC_ID_CALL_CONVENTION_MASK |
- FUNC_ID_ENTITY_MASK | FUNC_ID_FUNC_NUMBER_MASK,
-
- SMC_NUM_ARGS = 8, /* The last is optional hypervisor id. */
- SMC_NUM_RESULTS = 4,
-
- SMC_UNKNOWN_FUNC = 0xffffffff,
-};
-
-#define SMC_FUNC(entity, number, call_convention, call_type) \
- ((call_type) | (call_convention) | \
- ((entity) << FUNC_ID_ENTITY_SHIFT) | (number))
-
-#define SMC_FUNC_FAST(entity, number, call_convention) \
- SMC_FUNC((entity), (number), (call_convention), FUNC_ID_FASTCALL)
-
-#define SMC_FUNC_FAST32(entity, number) \
- SMC_FUNC_FAST((entity), (number), FUNC_ID_SMC32)
-
-#define SMC_FUNC_FAST64(entity, number) \
- SMC_FUNC_FAST((entity), (number), FUNC_ID_SMC64)
-
-struct smc_call {
- uint64_t args[SMC_NUM_ARGS];
- uint64_t results[SMC_NUM_RESULTS];
-};
-
-/* SMC immediate value needs to be 0. */
-/* Check mod AARCHx mode against calling convention. */
-
-static inline uint64_t smc64_arg(const struct smc_call *smc, unsigned i)
-{
- return smc->args[i];
-}
-
-static inline uint32_t smc32_arg(const struct smc_call *smc, unsigned i)
-{
- return smc64_arg(smc, i);
-}
-
-static inline void smc64_result(struct smc_call *smc, unsigned i, uint64_t v)
-{
- smc->results[i] = v;
-}
-
-static inline void smc32_result(struct smc_call *smc, unsigned i, uint32_t v)
-{
- uint64_t v64 = v;
- smc64_result(smc, i, v64);
-}
-
-static inline void smc32_return(struct smc_call *smc, int32_t v)
-{
- smc32_result(smc, 0, v);
-}
-
-static inline uint32_t smc_hypervisor_id(const struct smc_call *smc)
-{
- /* Set in W7 */
- return smc32_arg(smc, 7);
-}
-
-static inline uint32_t smc_session_id(const struct smc_call *smc)
-{
- /* Set in W6 */
- return smc32_arg(smc, 6);
-}
-
-static inline uint32_t smc_function_id(const struct smc_call *smc)
-{
- /* Function ID in W0. */
- return smc32_arg(smc, 0) & FUNC_ID_MASK;
-}
-
-/* Initialize the SMC layer. */
-void smc_init(void);
-
-/* Register a handler for a given function range, inclusive. */
-int smc_register_range(uint32_t min, uint32_t max, int (*)(struct smc_call *));
-
-#endif /* __ARCH_SMC_H__ */
diff --git a/src/arch/arm64/include/arch/startup.h b/src/arch/arm64/include/arch/startup.h
deleted file mode 100644
index 48f86f2..0000000
--- a/src/arch/arm64/include/arch/startup.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __ARCH_ARM64_INCLUDE_ARCH_STARTUP_H__
-#define __ARCH_ARM64_INCLUDE_ARCH_STARTUP_H__
-
-/* Every element occupies 8 bytes (64-bit entries) */
-#define PER_ELEMENT_SIZE_BYTES 8
-#define MAIR_INDEX 0
-#define TCR_INDEX 1
-#define TTBR0_INDEX 2
-#define SCR_INDEX 3
-#define VBAR_INDEX 4
-#define CNTFRQ_INDEX 5
-#define CPTR_INDEX 6
-#define CPACR_INDEX 7
-/* IMPORTANT!!! If any new element is added please update NUM_ELEMENTS */
-#define NUM_ELEMENTS 8
-
-#ifndef __ASSEMBLY__
-
-/*
- * startup_save_cpu_data is used to save register values that need to be setup
- * when a CPU starts booting. This is used by secondary CPUs as well as resume
- * path to directly setup MMU and other related registers.
- */
-void startup_save_cpu_data(void);
-
-#endif
-
-#endif /* __ARCH_ARM64_INCLUDE_ARCH_STARTUP_H__ */
diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h
index a0d121a..3d8d66c 100644
--- a/src/arch/arm64/include/armv8/arch/cpu.h
+++ b/src/arch/arm64/include/armv8/arch/cpu.h
@@ -24,18 +24,6 @@
static inline unsigned int smp_processor_id(void) { return 0; }
-/*
- * The arm64_cpu_startup() initializes CPU's exception stack and regular
- * stack as well initializing the C environment for the processor. Finally it
- * calls into c_entry.
- */
-void arm64_cpu_startup(void);
-
-/*
- * The arm64_arch_timer_init() initializes the CPU's cntfrq register of
- * ARM arch timer.
- */
-void arm64_arch_timer_init(void);
#if !defined(__PRE_RAM__)
struct cpu_driver { };
diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h
index 49ea747..c22d386 100644
--- a/src/arch/arm64/include/armv8/arch/exception.h
+++ b/src/arch/arm64/include/armv8/arch/exception.h
@@ -33,7 +33,6 @@
#include <arch/transition.h>
/* Initialize the exception handling on the current CPU. */
-void exception_hwinit(void);
void exception_init(void);
/*
diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h
index 8c5d2ea..83fd319 100644
--- a/src/arch/arm64/include/armv8/arch/lib_helpers.h
+++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h
@@ -62,10 +62,10 @@
#define SCR_EA_MASK (1 << SCR_EA_SHIFT)
#define SCR_EA_ENABLE (1 << SCR_EA_SHIFT)
#define SCR_EA_DISABLE (0 << SCR_EA_SHIFT)
-#define SCR_SMC_SHIFT 7
-#define SCR_SMC_MASK (1 << SCR_SMC_SHIFT)
-#define SCR_SMC_DISABLE (1 << SCR_SMC_SHIFT)
-#define SCR_SMC_ENABLE (0 << SCR_SMC_SHIFT)
+#define SCR_SMD_SHIFT 7
+#define SCR_SMD_MASK (1 << SCR_SMD_SHIFT)
+#define SCR_SMD_DISABLE (1 << SCR_SMD_SHIFT)
+#define SCR_SMD_ENABLE (0 << SCR_SMD_SHIFT)
#define SCR_HVC_SHIFT 8
#define SCR_HVC_MASK (1 << SCR_HVC_SHIFT)
#define SCR_HVC_DISABLE (0 << SCR_HVC_SHIFT)
diff --git a/src/arch/arm64/include/armv8/arch/smp/spinlock.h b/src/arch/arm64/include/armv8/arch/smp/spinlock.h
deleted file mode 100644
index 10278e7..0000000
--- a/src/arch/arm64/include/armv8/arch/smp/spinlock.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef ARCH_SMP_SPINLOCK_H
-#define ARCH_SMP_SPINLOCK_H
-
-#include <arch/barrier.h>
-#include <stdint.h>
-
-typedef struct {
- volatile uint32_t lock;
-} spinlock_t;
-
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
-#define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED;
-
-static inline void spin_lock(spinlock_t *spin)
-{
- while (1) {
- if (load_acquire_exclusive(&spin->lock) != 0)
- continue;
- if (store_release_exclusive(&spin->lock, 1))
- break;
- }
-}
-
-static inline void spin_unlock(spinlock_t *spin)
-{
- store_release(&spin->lock, 0);
-}
-
-#endif
diff --git a/src/arch/arm64/startup.c b/src/arch/arm64/startup.c
deleted file mode 100644
index 5208b10..0000000
--- a/src/arch/arm64/startup.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/lib_helpers.h>
-#include <arch/startup.h>
-#include <console/console.h>
-
-/* This space is defined in stage_entry.S. */
-extern u8 _arm64_startup_data[];
-
-static inline void save_element(size_t index, uint64_t val)
-{
- uint64_t *ptr = (uint64_t *)_arm64_startup_data;
-
- ptr[index] = val;
-}
-
-/*
- * startup_save_cpu_data is used to save register values that need to be setup
- * when a CPU starts booting. This is used by secondary CPUs as well as resume
- * path to directly setup MMU and other related registers.
- */
-void startup_save_cpu_data(void)
-{
- save_element(MAIR_INDEX, raw_read_mair_current());
- save_element(TCR_INDEX, raw_read_tcr_current());
- save_element(TTBR0_INDEX, raw_read_ttbr0_current());
- save_element(VBAR_INDEX, raw_read_vbar_current());
- save_element(CNTFRQ_INDEX, raw_read_cntfrq_el0());
- save_element(CPACR_INDEX, raw_read_cpacr_el1());
-
- if (get_current_el() == EL3) {
- save_element(SCR_INDEX, raw_read_scr_el3());
- save_element(CPTR_INDEX, raw_read_cptr_el3());
- }
-
- dcache_clean_by_mva(_arm64_startup_data,
- NUM_ELEMENTS * PER_ELEMENT_SIZE_BYTES);
-}
diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c
index efb0e88..25cfe59 100644
--- a/src/arch/arm64/transition.c
+++ b/src/arch/arm64/transition.c
@@ -17,8 +17,10 @@
* Foundation, Inc.
*/
+#include <arch/cache.h>
#include <arch/lib_helpers.h>
#include <arch/transition.h>
+#include <assert.h>
#include <console/console.h>
/* Litte-endian, No XN-forced, Instr cache disabled,
@@ -70,8 +72,6 @@ void transition_with_entry(void *entry, void *arg, struct exc_state *exc_state)
void transition(struct exc_state *exc_state)
{
- uint32_t scr_mask;
- uint64_t hcr_mask;
uint64_t sctlr;
uint32_t current_el = get_current_el();
@@ -93,23 +93,27 @@ void transition(struct exc_state *exc_state)
if (elx->spsr & SPSR_ERET_32)
die("ARM64 Error: Do not support eret to Aarch32\n");
- else {
- scr_mask = SCR_LOWER_AARCH64;
- hcr_mask = HCR_LOWER_AARCH64;
- }
- /* SCR: Write to SCR if current EL is EL3 */
- if (current_el == EL3) {
- uint32_t scr = raw_read_scr_el3();
- scr |= scr_mask;
- raw_write_scr_el3(scr);
- }
- /* HCR: Write to HCR if current EL is EL2 */
- else if (current_el == EL2) {
- uint64_t hcr = raw_read_hcr_el2();
- hcr |= hcr_mask;
- raw_write_hcr_el2(hcr);
- }
+ /* Most parts of coreboot currently don't support EL2 anyway. */
+ assert(current_el == EL3);
+
+ /* Initialize SCR with defaults for running without secure monitor. */
+ raw_write_scr_el3(SCR_TWE_DISABLE | /* don't trap WFE */
+ SCR_TWI_DISABLE | /* don't trap WFI */
+ SCR_ST_ENABLE | /* allow secure timer access */
+ SCR_LOWER_AARCH64 | /* lower level is AArch64 */
+ SCR_SIF_DISABLE | /* disable secure ins. fetch */
+ SCR_HVC_ENABLE | /* allow HVC instruction */
+ SCR_SMD_ENABLE | /* disable SMC instruction */
+ SCR_RES1 | /* reserved-1 bits */
+ SCR_EA_DISABLE | /* disable ext. abort trap */
+ SCR_FIQ_DISABLE | /* disable FIQ trap to EL3 */
+ SCR_IRQ_DISABLE | /* disable IRQ trap to EL3 */
+ SCR_NS_ENABLE); /* lower level is non-secure */
+
+ /* Initialize CPTR to not trap anything to EL3. */
+ raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE |
+ CPTR_EL3_TFP_DISABLE);
/* ELR/SPSR: Write entry point and processor state of program */
raw_write_elr_current(elx->elr);
@@ -122,6 +126,7 @@ void transition(struct exc_state *exc_state)
/* SP_ELx: Initialize stack pointer */
raw_write_sp_elx(elx->sp_elx, elx_el);
+ isb();
/* Eret to the entry point */
trans_switch(regs);
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 8473d4a..04d5783 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -17,11 +17,6 @@ config SOC_NVIDIA_TEGRA132
if SOC_NVIDIA_TEGRA132
-# TODO: Remove after replacing arch/arm64/stage_entry.S
-config STACK_SIZE
- hex
- default 0x1000
-
config MAINBOARD_DO_DSI_INIT
bool "Use dsi graphics interface"
depends on MAINBOARD_DO_NATIVE_VGA_INIT
@@ -36,10 +31,6 @@ config MAINBOARD_DO_SOR_INIT
help
Initialize dp display
-config MAX_CPUS
- int
- default 2
-
config MTS_DIRECTORY
string "Directory where MTS microcode files are located"
default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod"
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 22ccba5..b48fd3a 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -90,6 +90,7 @@ ramstage-y += ramstage.c
ramstage-y += mmu_operations.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += ../tegra/usb.c
+ramstage-y += stage_entry.S
modules_arm-y += monotonic_timer.c
diff --git a/src/soc/nvidia/tegra132/maincpu.S b/src/soc/nvidia/tegra132/maincpu.S
deleted file mode 100644
index 898d821..0000000
--- a/src/soc/nvidia/tegra132/maincpu.S
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <arch/asm.h>
-
-ENTRY(maincpu_setup)
- /*
- * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
- * aborts may happen early and crash before the abort handlers are
- * installed, but at least the problem will show up near the code that
- * causes it.
- */
- msr cpsr, #0xdf
-
- ldr sp, maincpu_stack_pointer
- eor lr, lr
- ldr r0, maincpu_entry_point
- bx r0
-ENDPROC(maincpu_setup)
-
- .align 2
-
- .global maincpu_stack_pointer
-maincpu_stack_pointer:
- .word 0
-
- .global maincpu_entry_point
-maincpu_entry_point:
- .word 0
diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c
index e019ce2..d3d874f 100644
--- a/src/soc/nvidia/tegra132/ramstage.c
+++ b/src/soc/nvidia/tegra132/ramstage.c
@@ -18,6 +18,7 @@
*/
#include <arch/stages.h>
+#include <gic.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/mc.h>
@@ -34,6 +35,10 @@ static void lock_down_vpr(void)
void arm64_soc_init(void)
{
+ /* TODO: Is this still needed? */
+ gic_init();
+
+ /* TODO: Move TrustZone setup to BL31? */
trustzone_region_init();
tegra132_mmu_init();
diff --git a/src/soc/nvidia/tegra132/stage_entry.S b/src/soc/nvidia/tegra132/stage_entry.S
new file mode 100644
index 0000000..c3e4acc
--- /dev/null
+++ b/src/soc/nvidia/tegra132/stage_entry.S
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/asm.h>
+
+ENTRY(stage_entry)
+ /* Initialize PSTATE, SCTLR and caches to clean state */
+ bl arm64_init_cpu
+
+ /* Load SP (this assumes earlier stages don't persist data on stack) */
+ ldr x0, =_estack
+ sub sp, x0, #16
+
+ /* Get some early init done that we want before starting the BSM */
+ bl arm64_soc_init
+
+ bl main
+ENDPROC(stage_entry)
diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig
index 002a6d3..5273d81 100644
--- a/src/soc/nvidia/tegra210/Kconfig
+++ b/src/soc/nvidia/tegra210/Kconfig
@@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA210
select ARCH_VERSTAGE_ARMV4
select ARCH_ROMSTAGE_ARMV4
select ARCH_RAMSTAGE_ARMV8_64
- select ARCH_ARM64_CPU_CORTEX_A57
select BOOTBLOCK_CONSOLE
select GIC
select HAVE_MONOTONIC_TIMER
@@ -22,11 +21,6 @@ if SOC_NVIDIA_TEGRA210
config CHROMEOS
select CHROMEOS_RAMOOPS_NON_ACPI
-# TODO: Remove after replacing arch/arm64/stage_entry.S
-config STACK_SIZE
- hex
- default 0x1000
-
config MAINBOARD_DO_DSI_INIT
bool "Use dsi graphics interface"
depends on MAINBOARD_DO_NATIVE_VGA_INIT
@@ -41,10 +35,6 @@ config MAINBOARD_DO_SOR_INIT
help
Initialize dp display
-config MAX_CPUS
- int
- default 4
-
choice CONSOLE_SERIAL_TEGRA210_UART_CHOICES
prompt "Serial Console UART"
default CONSOLE_SERIAL_TEGRA210_UARTA
diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c
index 6e51a8c..3b1cab9 100644
--- a/src/soc/nvidia/tegra210/cpu.c
+++ b/src/soc/nvidia/tegra210/cpu.c
@@ -27,7 +27,7 @@
static void enable_core_clocks(int cpu)
{
- const uint32_t cpu_clocks[CONFIG_MAX_CPUS] = {
+ const uint32_t cpu_clocks[] = {
[0] = CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_DBG0 |
CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CX0,
[1] = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 |
diff --git a/src/soc/nvidia/tegra210/maincpu.S b/src/soc/nvidia/tegra210/maincpu.S
deleted file mode 100644
index 898d821..0000000
--- a/src/soc/nvidia/tegra210/maincpu.S
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <arch/asm.h>
-
-ENTRY(maincpu_setup)
- /*
- * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
- * aborts may happen early and crash before the abort handlers are
- * installed, but at least the problem will show up near the code that
- * causes it.
- */
- msr cpsr, #0xdf
-
- ldr sp, maincpu_stack_pointer
- eor lr, lr
- ldr r0, maincpu_entry_point
- bx r0
-ENDPROC(maincpu_setup)
-
- .align 2
-
- .global maincpu_stack_pointer
-maincpu_stack_pointer:
- .word 0
-
- .global maincpu_entry_point
-maincpu_entry_point:
- .word 0
diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c
index 1671fdf..8b750a3 100644
--- a/src/soc/nvidia/tegra210/ramstage.c
+++ b/src/soc/nvidia/tegra210/ramstage.c
@@ -20,12 +20,13 @@
#include <arch/clock.h>
#include <arch/cpu.h>
#include <arch/stages.h>
+#include <gic.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/mmu_operations.h>
#include <soc/mtc.h>
-void arm64_arch_timer_init(void)
+static void arm64_arch_timer_init(void)
{
uint32_t freq = clock_get_osc_khz() * 1000;
// Set the cntfrq register.
@@ -53,9 +54,16 @@ static void mselect_enable_wrap(void)
void arm64_soc_init(void)
{
+ /* TODO: Is this still needed? */
+ gic_init();
+
+ /* TODO: Move arch timer setup to BL31? */
+ arm64_arch_timer_init();
+
/* Enable WRAP to INCR burst type conversion in MSELECT */
mselect_enable_wrap();
+ /* TODO: Move TrustZone setup to BL31? */
trustzone_region_init();
tegra210_mmu_init();
diff --git a/src/soc/nvidia/tegra210/stage_entry.S b/src/soc/nvidia/tegra210/stage_entry.S
index 66d8741..ffeaf21 100644
--- a/src/soc/nvidia/tegra210/stage_entry.S
+++ b/src/soc/nvidia/tegra210/stage_entry.S
@@ -86,10 +86,16 @@
ENTRY(stage_entry)
t210_a57_fixup
- b arm64_cpu_startup
-ENDPROC(stage_entry)
-ENTRY(tegra210_reset_handler)
- t210_a57_fixup
- b arm64_cpu_startup_resume
-ENDPROC(tegra210_reset_handler)
+ /* Initialize PSTATE, SCTLR and caches to clean state. */
+ bl arm64_init_cpu
+
+ /* Load SP (this assumes earlier stages don't persist data on stack) */
+ ldr x0, =_estack
+ sub sp, x0, #16
+
+ /* Get some early init done that we want before starting the BSM */
+ bl arm64_soc_init
+
+ bl main
+ENDPROC(stage_entry)
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