[coreboot-gerrit] New patch to review for coreboot: southbridge/amd/sr5650: Remove unnecessary register configuration

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11935

-gerrit

commit 2bcfcf474f61cc60c78ff359b57b815056d2e69e
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Sun Aug 2 21:29:20 2015 -0500

    southbridge/amd/sr5650: Remove unnecessary register configuration
    
    Change-Id: I432b942f114243cba23c9a8d916cf6d07bc4740b
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sr5650/early_setup.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index d91f3bd..ec555f8 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -437,7 +438,6 @@ static void sr5650_por_htiu_index_init(device_t nb_dev)
 	set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<2,  0x1<<2);
 	set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<4,  0x1<<4);
 
-	set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 0 << 21);
 	axindxc_reg(0x10, 1 << 9, 1 << 9);
 	set_pcie_enable_bits(nb_dev, 0x10 | 5 << 16, 1 << 9, 1 << 9);
 	set_htiu_enable_bits(nb_dev, 0x06, 0x1<<26, 0x1<<26);